ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 28

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

ADV7170/ADV7171
SUBCARRIER FREQUENCY REGISTER 3–0
(FSC3–FSC0)
(Address [SR4–SR0] = 09H–02H)
These 8-bit-wide registers are used to set up the subcarrier
frequency. The value of these registers is calculated by using the
following equation:
Subcarrier Frequency Register =
i.e.: NTSC Mode,
Subcarrier Frequency Value =
Figure 45 shows how the frequency is set up by the four registers.
SUBCARRIER PHASE REGISTER (FP7–FP0)
(Address [SR4–SR0] = 0DH)
This 8-bit-wide register is used to set up the subcarrier phase.
Each bit represents 1.41 . For normal operation this register is
set to 00Hex.
CLOSED CAPTIONING EVEN FIELD
DATA REGISTER 1–0 (CED15–CED00)
(Address [SR4–SR0] = 0E–0FH)
These 8-bit-wide registers are used to set up the closed captioning
extended data bytes on even fields. Figure 46 shows how the
high and low bytes are set up in the registers.
CLOSED CAPTIONING ODD FIELD
DATA REGISTER 1–0 (CCD15–CCD00)
(Subaddress [SR4–SR0] = 10–11H)
These 8-bit-wide registers are used to set up the closed
captioning data bytes on odd fields. Figure 47 shows how the
high and low bytes are set up in the registers.
SUBCARRIER
SUBCARRIER
SUBCARRIER
BYTE 0
SUBCARRIER
BYTE 0
Figure 46. Closed Captioning Extended Data Register
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
F
F
BYTE 1
BYTE 1
CLK
SCF
REG 3
REG 2
REG 1
REG 0
Figure 47. Closed Captioning Data Register
Figure 45. Subcarrier Frequency Register
= 3.5795454 MHz
= 27 MHz,
CCD7
CED7
CCD15
CED15
FSC23
FSC15
FSC31
FSC7
CCD6
CED6
CED14
CCD14
FSC22 FSC21
FSC14 FSC13
FSC30 FSC29
FSC6
CCD5
CED5
= 21F07C16HEX
CCD13
CED13
FSC5
27 10
CCD4
CED4
2
2
F
32
CCD12
32
CED12
CLK
–1
–1
FSC20
FSC12
FSC28
FSC4
CCD3
CED3
6
CCD11
CED11
F
3.5795454 10
FSC19
FSC11
SCF
FSC27
FSC3
CCD2
CED2
CCD10
CED10
FSC10
FSC18
FSC26
FSC2
CCD1
CED1
CCD9
CED9
FSC17
FSC25
FSC1
FSC9
CED0
CCD0
6
CCD8
CED8
FSC24
FSC16
FSC8
FSC0
–28–
NTSC PEDESTAL/PAL TELETEXT CONTROL
REGISTERS 3–0 (PCE15–0, PCO15–0)/(TXE15–0, TXO15–0)
(Subaddress [SR4–SR0] = 12–15H)
These 8-bit-wide registers are used to enable the NTSC pedes-
tal/PAL Teletext on a line-by-line basis in the vertical blanking
interval for both odd and even fields. Figures 48 and 49 show
the four control registers. A Logic “1” in any of the bits of these
registers has the effect of turning the Pedestal OFF on the
equivalent line when used in NTSC. A Logic “1” in any of the
bits of these registers has the effect of turning Teletext ON on
the equivalent line when used in PAL.
TELETEXT CONTROL REGISTER TC07 (TC07–TC00)
(Address [SR4–SR0] = 19H)
Teletext Control Register is an 8-bit-wide register. See Figure 50.
TTXREQ Rising Edge Control (TC07–TC04)
These bits control the position of the rising edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. See Figure 59.
TTXREQ Falling Edge Control (TC03–TC00)
These bits control the position of the falling edge of TTXREQ.
It can be programmed from zero CLOCK cycles to a max of 15
CLOCK cycles. This controls the active window for Teletext
data. Increasing this value reduces the amount of Teletext bits
below the default of 360. If Bits TC03-TC00 are 00Hex when
bits TC07–TC04 are changed, the falling edge of TTREQ will
track that of the rising edge (i.e., the time between the falling
and rising edge remains constant). See Figure 59.
CGMS_WSS REGISTER 0 C/W0 (C/W07–C/W00)
(Address [SR4–SR0] = 16H)
CGMS_WSS Register 0 is an 8-bit-wide register. Figure 51
shows the operations under the control of this register.
FIELD 1/3
FIELD 1/3
FIELD 1/3
FIELD 2/4
FIELD 2/4
FIELD 2/4
FIELD 2/4
FIELD 1/3
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 LINE 9
LINE 22 LINE 21 LINE 20 LINE 19 LINE 18 LINE 17 LINE 16 LINE 15
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15
PCE15
TXO15
TXE15
PCO7
PCE7
Figure 48. Pedestal Control Registers
TXO7
TXE7
Figure 49. Teletext Control Registers
PCO14
TXO14
PCE14
TXE14
PCO6
PCE6
TXO6
TXE6
PCO13
PCO5
PCE13
TXO13
TXE13
PCE5
TXO5
TXE5
PCO12
TXO12
PCO4
PCE12
TXE12
PCE4
TXO4
TXE4
PCO11
PCO3
TXO11
PCE11
TXE11
PCE3
TXO3
TXE3
PCO10
PCE10
TXO10
PCO2
TXE10
PCE2
TXO2
TXE2
LINE 8
LINE 8 LINE 7
PCO1
PCO9
PCE1
PCE9
TXO1
TXO9
TXE1
TXE9
LINE 7
REV. 0
PCO0
PCO8
PCE0
PCE8
TXO0
TXO8
TXE0
TXE8