ADV7170SU AD [Analog Devices], ADV7170SU Datasheet - Page 26

• Manufacturer Part Number: ADV7170SU
• Manufacturer: AD [Analog Devices]

ADV7170/ADV7171
MODE REGISTER 4 MR4 (MR47–MR40)
(Address (SR4–SR0) = 04H)
Mode Register 4 is a 8-bit-wide register.
Figure 42 shows the various operations under the control of
Mode Register 4.
MR4 BIT DESCRIPTION
Output Select (MR40)
This bit specifies if the part is in composite video or RGB/YUV
mode. Note that in RGB/YUV mode the composite signal is
still available.
RGB/YUV Control (MR41)
This bit enables the output from the RGB DACs to be set to
YUV output video standard.
RGB Sync (MR42)
This bit is used to set up the RGB outputs with the sync infor-
mation encoded on all RGB outputs.
VSYNC_3H Control (MR43)
When this bit is enabled (“1”) in slave mode, it is possible to
drive the VSYNC active low input for 2.5 lines in PAL mode
and 3 lines in NTSC mode. When this bit is enabled in mas-
ter mode, the ADV7170/ADV7171 outputs an active low
VSYNC signal for 3 lines in NTSC mode and 2.5 lines in PAL
mode.
ZERO SHOULD
BE WRITTEN TO
THIS BIT
REGISTER RESET
TR07
MR47
MR47
(0)
TIMING
TR07
MR46
SLEEP MODE
0
1
TR06
CONTROL
PIXEL PORT
0
1
CONTROL
MR46
DISABLE
ENABLE
TR06
MR45
8 BIT
16 BIT
FILTER CONTROL
0
1
ACTIVE VIDEO
ENABLE
DISABLE
MR45
TR05 TR04
MR44
TR05
0
0
1
1
0
1
Figure 43. Timing Register 0
Figure 42. Mode Register 4
PEDESTAL
LUMA DELAY
CONTROL
0
1
0
1
PEDESTAL OFF
PEDESTAL ON
MR44
TR04
0ns DELAY
74ns DELAY
148ns DELAY
222ns DELAY
MR43
TR03
–26–
0
1
BLACK INPUT
0
1
VSYNC_3H
MR43
CONTROL
TR03
Pedestal Control (MR44)
This bit specifies whether a pedestal is to be generated on
the NTSC composite video signal. This bit is invalid if the
ADV7170/ADV7171 is configured in PAL mode.
Active Video Filter Switching (MR45)
This bit controls the filter mode applied outside the active video
portion of the line. This filter ensures that the Sync rise and fall
times are always on spec regardless of which Luma filter is se-
lected. A Logic “1” enables this mode.
Sleep Mode Control (MR46)
When this bit is set (“1”) Sleep Mode is enabled. With this
mode enabled, the ADV7170/ADV7171 power consumption is
reduced to typically 200 nA. The I
and read from when the ADV7170/ADV7171 is in Sleep
Mode. If MR46 is set to a (“0”) when the device is in Sleep
Mode, the ADV7170/ADV7171 will come out of Sleep Mode
and resume normal operation. Also, if the RESET signal is
applied during Sleep Mode the ADV7170/ADV7171 will come
out of Sleep Mode and resume normal operation.
Reserved (MR47)
A Logical 0 should be written to this bit.
TIMING REGISTER 0 (TR07–TR00)
(Address [SR4–SR0] = 07H)
Figure 43 shows the various operations under the control of
Timing Register 0. This register can be read from as well as
written to.
DISABLE
ENABLE
ENABLE
DISABLE
MR42
0
1
TR02 TR01
RGB SYNC
0
0
1
1
MR42
TIMING MODE
DISABLE
ENABLE
TR02
SELECTION
MR41
0
1
0
1
0
1
CONTROL
RGB/YUV
MODE 0
MODE 1
MODE 2
MODE 3
MR41
RGB OUTPUT
YUV OUTPUT
TR01
MR40
TR00
0
1
0
1
MASTER/SLAVE
OUTPUT SELECT
MR40
CONTROL
SLAVE TIMING
MASTER TIMING
YC OUTPUT
RGB/YUV OUTPUT
TR00
2
C registers can be written to
REV. 0