DAC1405D750HW NXP [NXP Semiconductors], DAC1405D750HW Datasheet - Page 22

• Manufacturer Part Number: DAC1405D750HW
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1405D750_1
Preliminary data sheet
10.2.5 Recommended configuration
10.3.1 Dual-port mode
10.3.2 Interleaved mode
10.3 Input data
It is recommended that the following additional settings are used to obtain optimum
performance at up to 750 Msps
Table 31.
The setting applied to MODE_SEL (register 00h[3]; see
whether the DAC1405D750 operates in the Dual-port mode or in Interleaved mode (see
Table
Table 32.
The data input for Dual-port mode operation is shown in
DAC has its own independent data input. The data enters the input latch on the rising
edge of the internal clock signal and is transferred to the DAC latch.
The data input for the Interleaved mode operation is illustrated in
mode
Address
Dec
17
19
20
Bit 3 setting
0
1
Fig 5.
32).
operation”.
Dual-port mode
Recommended configuration
Mode selection
Q13 to Q0
Function
Dual port mode
Interleaved mode
All information provided in this document is subject to legal disclaimers.
I13 to I0
Hex
11h
13h
14h
Rev. 01 — 10 March 2010
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
LATCH
LATCH
Q
I
00001010
01101100
01101100
Value
Bin
active
I13 to I0
active
2 ×
2 ×
FIR 1
FIR 1
2 ×
2 ×
FIR 2
FIR 2
Dec
10
108
108
Q13 to Q0
active
off
Table 10 on page
Figure 5 “Dual-port
DAC1405D750
2 ×
2 ×
Figure 6 “Interleaved
FIR 3
FIR 3
001aal653
© NXP B.V. 2010. All rights reserved.
Pin 41
Q13
SELIQ
Hex
0Ah
6Ch
6Ch
17) defines
mode”. Each
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