DAC1405D750HW NXP [NXP Semiconductors], DAC1405D750HW Datasheet - Page 25

• Manufacturer Part Number: DAC1405D750HW
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1405D750_1
Preliminary data sheet
10.5.1 Timing when using the internal PLL (PLL on)
10.5.2 Timing when using an external PLL (PLL off)
10.6 FIR filters
In
The setting applied to PLL_DIV[1:0] (register 02h[4:3]; see
map”) allows the frequency between the digital part and the DAC core to be adjusted.
Table 33.
The settings applied to DAC_CLK_DELAY[1:0] (register 02h[2:1]) and DAC_CLK_POL
(register 02h[0]), allow adjustment of the phase and polarity of the sampling clock. This
occurs at the input of the DAC core and depends mainly on the sampling frequency. Some
examples are given in
Table 34.
It is recommended that a delay of 280 ps is used on the internal digital clock (CLK
obtain optimum device performance up to750 Msps.
Table 35.
The DAC1405D750 integrates three selectable Finite Impulse Response (FIR) filters
which enables the device to use 4× or 8× interpolation rates. All three interpolation filters
have a stop-band attenuation of at least 80 dBc and a pass-band ripple of less than
0.0005 dB. The coefficients of the interpolation filters are given in
filter
Mode
Dual Port
Dual Port
Interleaved
Interleaved
Mode
Dual Port
Dual Port
Address
Dec
2
Fig 10. Input timing diagram when internal PLL bypassed (off)
Table 33
coefficients”.
(SYNCP − SYNCN)
Frequencies
Sample clock phase and polarity examples
Optimum external PLL timing settings
Q13 to Q0
“Frequencies”, the links between internal and external clocking are defined.
I13 to I0/
Hex
02h
SYNC
All information provided in this document is subject to legal disclaimers.
CLK input
(MHz)
185
92.5
370
185
Input data rate
(MHz)
92.5
92.5
Table 34 “Sample clock phase and polarity
Rev. 01 — 10 March 2010
Register name
PLLCFG
Input data rate
(MHz)
185
92.5
370
185
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
90 %
t
Interpolation
4×
8×
su(i)
N
50 %
t
h(i)
90 %
Value
Digital clock delay Bin
280 ps
Interpolation
4×
8×
4×
8×
Update rate
(Msps)
370
740
N + 1
DAC1405D750
Table 9 “Register allocation
Update rate
(Msps)
740
740
740
740
DAC_CLK_
DELAY [1:0]
01
01
10001000
Table 36 “Interpolation
examples”.
© NXP B.V. 2010. All rights reserved.
N + 2
PLL_DIV[1:0]
01 (/ 4)
10 (/ 8)
00 (/ 2)
01 (/ 4)
Dec
136
DAC_CLK_
POL
0
0
001aal384
dig
88h
Hex
25 of 43
) to