DAC1405D750HW NXP [NXP Semiconductors], DAC1405D750HW Datasheet - Page 23

• Manufacturer Part Number: DAC1405D750HW
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1405D750_1
Preliminary data sheet
In Interleaved mode, both DACs use the same data input at twice the Dual-port mode
frequency. Data enters the latch on the rising edge of the internal clock signal. The data is
sent to either latch I or latch Q, depending on the SELIQ signal.
The SELIQ input (pin 41) allows the synchronization of the internally demultiplexed I and
Q channels; see
edge)”.
The SELIQ signal can be either synchronous or asynchronous (single rising edge, single
pulse). The first data following the SELIQ rising edge is sent in channel I and following
data is sent in channel Q. After this, data is distributed alternately between these
channels.
Fig 6.
Fig 7.
(asynchronous alternative 1)
(asynchronous alternative 2)
Interleaved mode operation
Interleaved mode timing (8x interpolation, latch on rising edge)
(synchronous alternative)
CLK
Q13/SELIQ
I13 to I0
dig
All information provided in this document is subject to legal disclaimers.
= internal digital clock
Figure 7 “Interleaved mode timing (8x interpolation, latch on rising
Latch Q output
Latch I output
Rev. 01 — 10 March 2010
CLK
SELIQ
SELIQ
SELIQ
dig
In
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
LATCH
LATCH
Q
I
N
N + 1
XX
XX
2 ×
2 ×
FIR 1
FIR 1
N + 2
2 ×
2 ×
FIR 2
FIR 2
N + 3
N + 1
N
DAC1405D750
N + 4
2 ×
2 ×
FIR 3
FIR 3
© NXP B.V. 2010. All rights reserved.
N + 5
N + 2
N + 3
001aal654
001aaj814
23 of 43