DAC1405D750HW NXP [NXP Semiconductors], DAC1405D750HW Datasheet - Page 24

• Manufacturer Part Number: DAC1405D750HW
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1405D750_1
Preliminary data sheet
10.4 Input clock
10.5 Timing
The DAC1405D750 can operate at the following clock frequencies:
The input clock is LVDS compliant (see
differential sine wave signal (see
The DAC1405D750 can operate at a sampling frequency (f
data rate (f
to the CLK signal. When the internal PLL is bypassed, the SYNC signal is used as a
reference. The input timing in the second case is shown in
when internal PLL bypassed
Fig 8.
Fig 9.
PLL on: up to 185 MHz in Dual-port mode and up to 370 MHz in Interleaved mode
PLL off: up to 750 MHz
LVDS clock configuration
Interfacing CML to LVDS
data
) up to 185 MHz. When using the internal PLL, the input data is referenced
All information provided in this document is subject to legal disclaimers.
CML
Rev. 01 — 10 March 2010
Z = 50 Ω
Z = 50 Ω
Dual 14-bit DAC, up to 750 Msps; 4× and 8× interpolating
(off)”.
LVDS
Z = 50 Ω
Z = 50 Ω
Figure
Zdiff =
100 Ω
100 nF
100 nF
V
DDA(1V8)
AGND
Figure
9).
1.1 kΩ
2.2 kΩ
Zdiff =
100 Ω
CLKN
CLKP
55 Ω
55 Ω
8) but it can also be interfaced with CML
100 nF
CLKN
CLKP
001aah021
Figure 10 “Input timing diagram
LVDS
s
DAC1405D750
) up to 750 Msps with an input
001aah020
LVDS
© NXP B.V. 2010. All rights reserved.
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