DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 31

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
DAC1408D650
Preliminary data sheet
10.11 Analog output
(register 0Ch; see
register 0Eh; see
the range of variation of the digital offset (see
Table 16.
Default settings are shown highlighted.
The DAC1408D650 has two output channels each of which produces two complementary
current outputs. These allow the even-order harmonics and noise to be reduced. The pins
are IOUTAP/IOUTAN and IOUTBP/IOUTBN respectively and need to be connected via a
load resistor R
For the equivalent analog output circuit of one DAC, refer to
consists of a parallel combination of NMOS current sources, and their associated
switches, for each segment.
The cascode source configuration increases the output impedance of the source, thus
improving the dynamic performance of the DAC by introducing less distortion.
The device can provide an output level of up to 2 V
following stages and the targeted performances.
DAC_OFFSET[11:0]
Decimal
−2048
−2047
...
−1
0
+1
...
+2046
+2047
Fig 19. Equivalent analog output circuit (one DAC)
Digital offset adjustment
L
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
to the 3.3 V analog power supply (V
Table 33 “DAC_B_CFG_3 register (address 0Eh) bit
Table 31 “DAC_B_CFG_1 register (address 0Ch) bit description”
Rev. 02 — 11 August 2010
AGND
Two’s complement
1000 0000 0000
1000 0000 0001
...
1111 1111 1111
0000 0000 0000
0000 0000 0001
...
0111 1111 1110
0111 1111 1111
AGND
Table
IOUTAP/IOUTBP
IOUTAN/IOUTBN
o(p-p)
16).
DDA(3V3)
, depending on the application, the
DAC1408D650
).
Offset applied
−4096
−4094
...
−2
0
+2
...
+4092
+4094
Figure
V
DDA(3V3)
R L
001aah019
19. This circuit
R L
description”) define
© NXP B.V. 2010. All rights reserved.
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and