DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 58

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 80.
Default settings are shown highlighted.
Table 81.
Default settings are shown highlighted.
Table 82.
Default settings are shown highlighted.
DAC1408D650
Preliminary data sheet
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
3
2
1
0
Bit
7
6
5
4
Symbol
SR_SWA_LN3
SR_SWA_LN2
SR_SWA_LN1
SR_SWA_LN0
SR_CA_LN3
SR_CA_LN2
SR_CA_LN1
SR_CA_LN0
Symbol
SR_CNTRL_LN3
SR_CNTRL_LN2
SR_CNTRL_LN1
SR_CNTRL_LN0
SR_DEC_LN3
SR_DEC_LN2
SR_DEC_LN1
SR_DEC_LN0
Symbol
FORCE_LOCK_LN3
FORCE_LOCK_LN2
FORCE_LOCK_LN1
FORCE_LOCK_LN0
10.15.2.8 Page 4 bit definition detailed description
SR_DLP_0 register (address 00h) bit description
SR_DLP_1 register (address 01h) bit description
FORCE_LOCK register (address 02h) bit description
Please refer to
tables, all the values emphasized in bold are the default values.
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
Table 79
All information provided in this document is subject to legal disclaimers.
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
R/W
R/W
R/W
R/W
Rev. 02 — 11 August 2010
for a register overview and their default values. In the following
Value
Value
0
0
0
0
Value
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
Description
Description
soft reset decoder_10b8b lane 3
soft reset decoder_10b8b lane 2
soft reset decoder_10b8b lane 1
soft reset decoder_10b8b lane 0
Description
lane 3 lock mode
lane 2 lock mode
lane 1 lock mode
lane 0 lock mode
softreset sync_word_alignment lane 3
softreset sync_word_alignment lane 2
softreset sync_word_alignment lane 1
softreset sync_word_alignment lane 0
softreset clock_alignment lane 3
softreset clock_alignment lane 2
softreset clock_alignment lane 1
softreset clock_alignment lane 0
soft reset controller lane 3
soft reset controller lane 2
soft reset controller lane 1
soft reset controller lane 0
automatic lock sync_word_alignment lane 3
manual lock sync_word_alignment lane 3
automatic lock sync_word_alignment lane 2
manual lock sync_word_alignment lane 2
automatic lock sync_word_alignment lane 1
manual lock sync_word_alignment lane 1
automatic lock sync_word_alignment lane 0
manual lock sync_word_alignment lane 0
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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