DAC1408D650C1 NXP [NXP Semiconductors], DAC1408D650C1 Datasheet - Page 80

• Manufacturer Part Number: DAC1408D650C1
• Description: Dual 14-bit DAC up to 650 Msps 2, 4 or 8 interpolating
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 152. LN0_CFG_8 register (address 08h) bit description
Default settings are shown highlighted.
Table 153. LN0_CFG_9 register (address 09h) bit description
Default settings are shown highlighted.
Table 154. LN0_CFG_10 register (address 0Ah) bit description
Default settings are shown highlighted.
Table 155. LN0_CFG_11 register (address 0Bh) bit description
Default settings are shown highlighted.
Table 156. LN0_CFG_12 register (address 0Ch) bit description
Default settings are shown highlighted.
Table 157. LN0_CFG_13 register (address 0Dh) bit description
Default settings are shown highlighted.
Table 158. LN1_CFG_0 register (address 10h) bit description
Default settings are shown highlighted.
Table 159. LN1_CFG_1 register (address 11h) bit description
Default settings are shown highlighted.
Table 160. LN1_CFG_2 register (address 12h) bit description
Default settings are shown highlighted.
DAC1408D650
Preliminary data sheet
Bit
4 to 0
Bit
4 to 0
Bit
7
4 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
7 to 0
Bit
3 to 0
Bit
4 to 0
Symbol
LN0_N’[4:0]
Symbol
LN0_S[4:0]
Symbol
LN0_HD
LN0_CF[4:0]
Symbol
LN0_RES1[7:0]
Symbol
LN0_RES2[7:0]
Symbol
LN0_FCHK[7:0]
Symbol
LN1_DID[7:0]
Symbol
LN1_BID[3:0]
Symbol
LN1_LID[4:0]
DAC1408D; up to 650 Msps; 2×, 4× or 8× interpolating with JESD204A
All information provided in this document is subject to legal disclaimers.
Access
R
Access
R
Access
R
R
Access
R
Access
R
Access
R
Access
R
Access
R
Access
R
Rev. 02 — 11 August 2010
Value
-
Value
-
Value
-
-
Value
-
Value
-
Value
Value
-
Value
-
Value
-
-
Description
number of bits per sample
Description
number of samples per converter per frame cycle
Description
high density
number of control words per frame cycle
Description
lane 0 reserved field
Description
lane 0 reserved field
Description
Description
lane1 device ID
Description
lane 1 bank ID
Description
lane 1 lane ID
lane 0 checksum
DAC1408D650
© NXP B.V. 2010. All rights reserved.
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