ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 14

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF522/523/524/525/526/527
Vertical Blanking Interval Mode
In this mode, the PPI only transfers vertical blanking interval
(VBI) data.
Entire Field Mode
In this mode, the entire incoming bit stream is read in through
the PPI. This includes active video, control preamble sequences,
and ancillary data that may be embedded in horizontal and ver-
tical blanking intervals. Data transfer starts immediately after
synchronization to Field 1. Data is transferred to or from the
synchronous channels through eight DMA engines that work
autonomously from the processor core.
USB ON-THE-GO DUAL-ROLE DEVICE
CONTROLLER
The USB clock (USB_XI) is provided through a dedicated exter-
nal crystal or crystal oscillator. See
On-The-Go—Receive and Transmit Timing on Page 54
related timing requirements. If using a crystal to provide the
USB clock, use a parallel-resonant, fundamental mode, micro-
processor-grade crystal.
The USB on-the-go dual-role device controller includes a phase
locked loop with programmable multipliers to generate the nec-
essary internal clocking frequency for USB. The multiplier value
should be programmed based on the USB_XI frequency to
achieve the necessary 480 MHz internal clock for USB high
speed operation. For example, for a USB_XI crystal frequency of
24 MHz, the USB_PLLOSC_CTRL register should be pro-
grammed with a multiplier value of 20 to generate a 480 MHz
internal clock.
CODE SECURITY WITH LOCKBOX SECURE
TECHNOLOGY
A security system consisting of a blend of hardware and soft-
ware provides customers with a flexible and rich set of code
security features with Lockbox secure technology. Key features
include:
The security scheme is based upon the concept of authentica-
tion of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets. See
claimer on Page
DYNAMIC POWER MANAGEMENT
The processor provides five operating modes, each with a differ-
ent performance/power profile. In addition, dynamic power
management provides the control functions to dynamically alter
the processor core supply voltage, further reducing power dissi-
pation. When configured for a 0 volt core supply voltage, the
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
21.
Lockbox Secure Technology Dis-
Universal Serial Bus (USB)
Rev. PrG | Page 14 of 80 | February 2009
for
processor enters the hibernate state. Control of clocking to each
of the processor peripherals also reduces power consumption.
See
Full-On Operating Mode—Maximum Performance
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum per-
formance can be achieved. The processor core and all enabled
peripherals run at full speed.
Active Operating Mode—Moderate Dynamic Power
Savings
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. DMA
access is available to appropriately configured L1 memories.
In the active mode, it is possible to disable the control input to
the PLL by setting the PLL_OFF bit in the PLL control register.
This register can be accessed with a user-callable routine in the
on-chip ROM called bfrom_SysControl(). If disabled, the PLL
control input must be re-enabled before transitioning to the
full-on or sleep modes.
Table 4. Power Settings
For more information about PLL controls, see the “Dynamic
Power Management” chapter in the ADSP-BF542x Blackfin
Processor Hardware Reference.
Sleep Operating Mode—High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity wakes up the processor.
When in the sleep mode, asserting a wakeup enabled in the
SIC_IWRx registers causes the processor to sense the value of
the BYPASS bit in the PLL control register (PLL_CTL). If
BYPASS is disabled, the processor transitions to the full on
mode. If BYPASS is enabled, the processor transitions to the
active mode.
System DMA access to L1 memory is not supported in
sleep mode.
Mode/State PLL
Full On
Active
Sleep
Deep Sleep
Hibernate
Table 4
for a summary of the power settings for each mode.
Enabled No
Enabled/
Disabled
Enabled —
Disabled —
Disabled —
Preliminary Technical Data
PLL
Bypassed
Yes
Core
Clock
(CCLK)
Enabled Enabled On
Enabled Enabled On
Disabled Enabled On
Disabled Disabled On
Disabled Disabled Off
System
Clock
(SCLK)
Core
Power