ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 57

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ADSP-BF522

Manufacturer Part Number
ADSP-BF522
Description
Blackfin Embedded Processor
Manufacturer
AD [Analog Devices]
Datasheet

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Preliminary Technical Data
Timer Clock Timing
Table 46
Table 46. Timer Clock Timing
Up/Down Counter/Rotary Encoder Timing
Table 47. Up/Down Counter/Rotary Encoder Timing
1
Parameter
Switching Characteristic
t
Parameter
Timing Requirements
t
t
t
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
TODP
WCOUNT
CIS
CIH
and
Figure 31
CUD/CDG/CZM
Timer Output Update Delay After PPI_CLK High
Up/Down Counter/Rotary Encoder Input Pulse Width
Counter Input Setup Time Before CLKOUT Low
Counter Input Hold Time After CLKOUT Low1
CLK OUT
TMRx OUTPUT
describe timer clock timing.
PPI_CLK
Figure 32. Up/Down Counter/Rotary Encoder Timing
Rev. PrG | Page 57 of 80 | February 2009
t
CIS
Figure 31. Timer Clock Timing
t
WCOUNT
1
t
CIH
t
SCLK
Min
Min
4.0
4.0
ADSP-BF522/523/524/525/526/527
V
V
+ 1
DDEXT
DDEXT
= 1.8 V
= 1.8 V
t
TODP
Max
12.0
Max
t
SCLK
Min
V
Min
V
4.0
4.0
DDEXT
DDEXT
+ 1
= 2.5/3.3 V
= 2.5/3.3 V
Max
12.0
Max
Unit
ns
Unit
ns
ns
ns

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