ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 59

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Preliminary Technical Data
HOSTDP A/C Timing- Host Write Cycle
Table 49
requirements.
Table 49. Host Write Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
NM (Not Measured) — This parameter is not measured, because the time for which HOST_ACK is low is system design dependent.
SADWRL
HADWRH
WRWL
WRWH
DWRHRDY
HDATWH
SDATWH
DRDYWRL
RDYPWR
describes the HOSTDP A/C Host Write Cycle timing
HOST_ADDR/HOST_CE Setup
before HOST_WR falling edge
HOST_ADDR/HOST_CE Hold
after HOST_WR rising edge
HOST_WR pulse width low
(ACK mode)
HOST_WR pulse width low
(INT mode)
HOST_WR pulse width high
or time between HOST_WR
rising edge and HOST_RD
falling edge
HOST_WR rising edge delay
after HOST_ACK rising edge
(ACK mode)
Data Hold after HOST_WR
rising edge
Data Setup before HOST_WR
rising edge
HOST_ACK low delay after
HOST_WR/HOST_CE asserted
(ACK mode)
HOST_ACK low pulse-width for
Write access (ACK mode)
HOST_ADDR
HOST_D15-0
HOST_CE
HOST_ACK
HOST_WR
t
1.5 t
t
DRDYWRL
t
2 t
RDYPRD
DWRHRDY
+ 8.7
Min
V
2.5
2.5
2.5
Rev. PrG | Page 59 of 80 | February 2009
4
0
t
DDEXT
SADWRL
SCLK
Figure 34. HOSTDP A/C- Host Write Cycle
SCLK
+
+
t
DRDYWRL
ADSP-BF522/524/526
= 1.8 V
1.5 t
Max
NM
t
1
SDATWH
SCLK
1.5 t
t
t
t
RDYPWR
t
DRDYWRL
t
2 t
V
WRWL
RDYPRD
DWRHRDY
+ 8.7
DDEXT
Min
2.5
2.5
2.5
4
0
SCLK
SCLK
+
= 2.5/3.3 V
+
1.5 t
t
DWRHRDY
ADSP-BF522/523/524/525/526/527
Max
NM
SCLK
1
t
HADWRH
t
WRWH
t
1.5 t
t
DRDYWRL
t
2 t
RDYPRD
DWRHRDY
+ 8.7
Min
V
2.5
2.5
2.5
t
4
0
HDATWH
DDEXT
SCLK
SCLK
+
+
ADSP-BF523/525/527
= 1.8 V
1.5 t
Max
NM
1
SCLK
t
1.5 t
t
DRDYWRL
t
2 t
V
RDYPRD
DWRHRDY
+ 8.7
DDEXT
Min
2.5
2.5
2.5
4
0
SCLK
SCLK
+
= 2.5/3.3 V
+
1.5 t
Max
NM
1
SCLK
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns