ADSP-BF522 AD [Analog Devices], ADSP-BF522 Datasheet - Page 56

• Manufacturer Part Number: ADSP-BF522
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF522/523/524/525/526/527
Timer Cycle Timing
Table 45
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
Table 45. Timer Cycle Timing
1
2
Parameter
Timing Characteristics
t
t
t
t
Switching Characteristics
t
t
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
WL
WH
TIS
TIH
HTO
TOD
and
Timer Pulse Width Input
Low (Measured In SCLK
Cycles)
Timer Pulse Width Input
High (Measured In SCLK
Cycles)
Timer Input Setup Time
Before CLKOUT Low
Timer Input Hold Time
After CLKOUT Low
Timer Pulse Width Output
(Measured In SCLK Cycles)
Timer Output Update
Delay After CLKOUT High
SCLK
Figure 30
/2) MHz.
TMRX OUTPUT
1
1
TMRx INPUT
CLKOUT
describe timer expired operations. The
2
2
Min
t
t
t
SCLK
SCLK
–2
V
SCLK
5
DDEXT
= 1.8 V
ADSP-BF522/524/526
(2
Rev. PrG | Page 56 of 80 | February 2009
32
Max
–1)t
8.1
t
TIS
SCLK
Figure 30. Timer Cycle Timing
V
t
Min
WH,
t
t
t
DDEXT
SCLK
SCLK
–2
SCLK
5
t
t
WL
TIH
= 2.5/3.3 V
(2
32
Max
–1)t
8.1
SCLK
t
SCLK
Min
t
t
8.1
SCLK
SCLK
–2
V
DDEXT
–1
Preliminary Technical Data
= 1.8 V
t
ADSP-BF523/525/527
HTO
(2
t
TOD
32
Max
–1)t
6
SCLK
t
V
SCLK
Min
t
t
DDEXT
6.2
–2
SCLK
SCLK
–1
= 2.5/3.3 V
(2
32
Max
–1)t
6
SCLK
Unit
ns
ns
ns
ns
ns
ns