ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 27

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Table 16. System Clock Requirements
Table 17. Clock Input and Reset Timing
1
2
3
Parameter
f
f
f
f
Parameter
Timing Requirements
t
t
t
t
t
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
Applies to bypass mode and nonbypass mode.
Applies after power-up sequence is complete. At power-up, the processor’s internal phase-locked loop requires no more than 2000 CLKIN cycles while RESET is asserted,
SCLK
SCLK
SCLK
SCLK
CKIN
CKINL
CKINH
BUFDLAY
WRST
by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400 MHz speed grade parts can not use the full CLKIN period range.
assuming stable power supplies and CLKIN (not including start-up time of external clock oscillator).
CLKBUF
CLKIN
RESET
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
CLKIN to CLKBUF Delay
RESET Asserted Pulse Width Low
Condition
V
V
V
V
DDEXT
DDEXT
DDEXT
DDEXT
3.3 V, V
3.3 V, V
2.5 V, V
2.5 V, V
t
CKINL
1
DDINT
DDINT
DDINT
DDINT
t
2
CKIN
2
t
CKINH
1.14 V
1.14 V
1.14 V
1.14 V
3
Rev. B | Page 27 of 68 | July 2006
Figure 9. Clock and Reset Timing
t
WRST
ADSP-BF534/ADSP-BF536/ADSP-BF537
VCO
, f
t
BUFDLAY
CCLK
, and f
SCLK
settings discussed in
Min
Min
25.0
10.0
10.0
11 t
CKIN
t
BUFDLAY
Table 12
Max
133
100
133
100
Max
100.0
10
through
Table
16. Since
Unit
ns
ns
ns
ns
ns
Unit
MHz
MHz
MHz
MHz