ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 54

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

ADSP-BF534/ADSP-BF536/ADSP-BF537
TEST CONDITIONS
All timing parameters appearing in this data sheet were
measured under the conditions described in this section.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram
t
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time t
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time t
the equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by V is dependent on the capacitive load, C
load current, I
the equation:
The output disable time t
t
t
switches to when the output voltage decays V from the mea-
sured output-high or output-low voltage. The time t
calculated with test loads C
ENA_MEASURED
DIS_MEASURED
DIS_MEASURED
and t
is the interval from when the reference signal
is the interval from when the reference signal
L
. This decay time can be approximated by
t
DECAY
ENA
t
DECAY
=
as shown in
ENA
DIS
t
ENA_MEASURED
L
is the difference between
and I
is calculated as shown in
=
TRIP
C
(Figure
is the interval from when the
L
L
, and with V equal to 0.5 V.
Figure
V
ENA
–
47). The time
I
t
L
is the interval from
TRIP
47. The time
DECAY
Rev. B | Page 54 of 68 | July 2006
L
and the
is
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. A
typical V is 0.4 V. C
and I
The hold time is t
example, t
(MEASURED)
(MEASURED)
t
DIS
V
V
OUTPUT
L
OH
OL
INPUT
Figure 49. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
OUTPUT
is the total leakage or three-state current (per data line).
OUTPUT STOPS DRIVING
OR
Figure 48. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
PIN
TO
DSDAT
V
MEAS
DECAY
for an SDRAM write cycle).
REFERENCE
t
V
DECAY
Figure 47. Output Enable/Disable
V
DIS_MEASURED
OH
OL
SIGNAL
using the equation given above. Choose V
t
(MEASURED)
DECAY
L
(MEASURED) + V
is the total bus capacitance (per data line),
plus the minimum disable time (for
HIGH IMPEDANCE STATE
30pF
t
ENA
V
50
OUTPUT STARTS DRIVING
t
ENA_MEASURED
V
V
TRIP
TRIP
t
TRIP
V
(HIGH)
V
(LOW)
OH
OL
V
(MEASURED)
V
(MEASURED)
LOAD
MEAS