ADSP-BF537 AD [Analog Devices], ADSP-BF537 Datasheet - Page 41

• Manufacturer Part Number: ADSP-BF537
• Description: Blackfin Embedded Processor
• Manufacturer: AD [Analog Devices]

Serial Peripheral Interface Port—Slave Timing
Table 29
Table 29. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICHS
SPICLS
SPICLK
HDS
SPITDS
SDSCI
SSPID
DSOE
DSDHI
DDSPID
HDSPID
HSPID
and
CPHA = 1
CPHA = 0
Figure 23
(INPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(CPOL = 0)
(CPOL = 1)
SPISS
MOSI
MOSI
(INPUT)
(INPUT)
MISO
MISO
SCK
SCK
Serial Clock High Period
Serial Clock Low Period
Serial Clock Period
Last SCK Edge to SPISS Not Asserted
Sequential Transfer Delay
SPISS Assertion to First SCK Edge
Data Input Valid to SCK Edge (Data Input Setup)
SCK Sampling Edge to Data Input Invalid
SPISS Assertion to Data Out Active
SPISS Deassertion to Data High Impedance
SCK Edge to Data Out Valid (Data Out Delay)
SCK Edge to Data Out Invalid (Data Out Hold)
describe SPI port slave operations.
t
DSOE
t
DSOE
t
SDSCI
MSB VALID
t
t
t
DDSPID
t
SPICHS
SPICLS
MSB VALID
SSPID
t
DDSPID
MSB
Figure 23. Serial Peripheral Interface (SPI) Port—Slave Timing
t
t
MSB
SPICLS
SPICHS
t
HDSPID
t
Rev. B | Page 41 of 68 | July 2006
HSPID
t
SSPID
ADSP-BF534/ADSP-BF536/ADSP-BF537
t
LSB VALID
DDSPID
t
t
SSPID
SPICLK
LSB
LSB VALID
t
HSPID
t
t
t
DSDHI
HDS
LSB
DSDHI
t
HSPID
Min
2 t
2 t
4 t
2 t
2 t
2 t
1.6
1.6
0
0
0
0
t
SPITDS
SCLK
SCLK
SCLK
SCLK
SCLK
SCLK
–1.5
–1.5
–1.5
–1.5
–1.5
–1.5
Max
8
8
10
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns