SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 126

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Table 100 Subaddress 7CH
Table 101 Subaddresses 7EH and 7FH
Table 102 Subaddresses 81H to 83H
Table 103 Subaddress 84H
2004 Jun 29
TTX60
TTXO
LINE
PCL
DCLK
PCLSY
IFRA
IFBP
PCLE
PCLI
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
HD-CODEC
individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate)
defines the frequency of the synthesized pixel clock PIXCLKO;
640
f
PIXCLK
this bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE
LOGIC
LEVEL
LOGIC
LEVEL
0
1
0
1
480 to PAL B/G: PCL = 1B5A73H (as by strapping pins)
0
1
0
1
0
1
0
1
=
PCL
---------- -
2
24
enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset
enables world standard teletext 60 Hz (FISE = 1)
new teletext protocol selected; at each rising edge of TTXRQ a single teletext bit is
requested (see Fig.51); default after reset
old teletext protocol selected; the encoder provides a window of TTXRQ going HIGH;
the length of the window depends on the chosen teletext standard (see Fig.51)
pixel clock input is differential, pin PIXCLKI receives the inverted clock; default after
reset
pixel clock input is single ended, pin PIXCLKI has no function
pixel clock generator runs free; default after reset
pixel clock generator gets synchronized with the vertical sync
input FIFO gets reset explicitly at falling edge
input FIFO gets reset every field; default after reset
input FIFO is active
input FIFO is bypassed; default after reset
controls the divider for the external pixel clock; see Table 104
controls the divider for the internal pixel clock; see Table 105
f
XTAL
8
; f
XTAL
= 27 MHz nominal, e.g. 640
126
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
SAA7108AE; SAA7109AE
480 to NTSC M: PCL = 20F63BH;
Product specification