SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 49

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9.1.4
The prefiltered luminance signal is fed to the
synchronization stage. Its bandwidth is further reduced to
1 MHz by a low-pass filter. The sync pulses are sliced and
fed to the phase detectors where they are compared with
the sub-divided clock frequency. The resulting output
signal is applied to the loop filter to accumulate all phase
deviations. Internal signals (e.g. HCL and HSY) are
generated in accordance with analog front-end
requirements. The loop filter signal drives an oscillator to
generate the line frequency control signal (LFCO);
see Fig.28.
The detection of ‘pseudo syncs’ as part of the Macrovision
copy protection standard is also done within the
synchronization circuit.
The result is reported as flag COPRO within the decoder
status byte at subaddress 1FH.
9.1.5
The internal CGC generates all clock signals required for
the video input processor.
9.1.6
A missing clock, insufficient digital or analog V
are forced to 3-state (see Fig.29). The indicator output RESd is LOW for approximately 128 LLC after the internal reset
and can be applied to reset other circuits of the digital TV system.
It is possible to force a reset by pulling the Chip Enable (CE) to ground. After the rising edge of CE and sufficient power
supply voltage, the outputs LLC, LLC2 and SDAd return from 3-state to active, while the other signals have to be
activated via programming.
2004 Jun 29
HD-CODEC
S
C
P
YNCHRONIZATION
OWER
LOCK GENERATION CIRCUIT
LFCO
-
ON RESET AND
BAND PASS
FC = LLC/4
CE
Fig.28 Block diagram of the clock generation circuit.
INPUT
DETECTION
CROSS
ZERO
DDAd
supply voltages (below 2.7 V) will start the reset sequence; all outputs
DETECTION
PHASE
49
The internal signal LFCO is a digital-to-analog converted
signal provided by the horizontal PLL. It is a multiple of the
line frequency:
The LFCO signal is multiplied internally by a factor of
2 and 4 in the PLL circuit (including phase detector, loop
filtering, VCO and frequency divider) to obtain the output
clock signals. The rectangular output clocks have a 50 %
duty cycle.
Table 16 Decoder clock frequencies
XTAL
LLC
LLC2
LLC4 (internal)
LLC8 (virtual)
6.75 MHz = 429
6.75 MHz = 432
CLOCK
DIVIDER
FILTER
LOOP
1/2
SAA7108AE; SAA7109AE
f
f
H
H
(50 Hz), or
(60 Hz).
OSCILLATOR
DIVIDER
1/2
MHB330
FREQUENCY (MHz)
24.576 or 32.110
Product specification
3.375
13.5
6.75
LLC
LLC2
27