SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 33

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
9.1.2.1
The clamping control circuit controls the correct clamping
of the analog input signals. A coupling capacitor is used to
store and filter the clamping voltage. An internal digital
clamp comparator generates the information with respect
to clamp-up or clamp-down. The clamping levels for the
two ADC channels are fixed for luminance (60) and
chrominance (128). Clamping time in normal use is set
with the HCL pulse at the back porch of the video signal.
9.1.2.2
The gain control circuit receives (via the I
gain levels for the two analog amplifiers, or controls one of
these amplifiers automatically via a built-in Automatic Gain
Control (AGC) as part of the Analog Input Control (AICO).
2004 Jun 29
HD-CODEC
Fig.13 Analog line with clamp (HCL) and gain
255
Clamping
Gain control
60
range (HSY).
1
analog line blanking
GAIN
HSY
TV line
CLAMP
HCL
2
C-bus) the static
MGL065
33
The AGC (automatic gain control for luminance) is used to
amplify a CVBS or Y signal to the required signal
amplitude, which is matched to the ADCs input voltage
range. The AGC active time is the sync bottom of the video
signal.
Signal (white) peak control limits the gain at signal
overshoots. The influence of supply voltage variation
within the specified range is automatically eliminated by
clamping and automatic gain control. The flow charts show
more details of the AGC; see Figs 16 and 17.
(1 V (p-p) 18/56 )
Fig.14 Automatic gain range.
SAA7108AE; SAA7109AE
analog input level
0 dB
3 dB
6 dB
maximum
minimum
range 9 dB
Product specification
ADC input level
MHB325
controlled
0 dB