SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 22

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
Other manipulations used for the Macrovision anti-taping
process, such as additional insertion of AGC super-white
pulses (programmable in height), are supported by the
SAA7108AE only.
To enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, thereby providing luminance in a 10-bit resolution.
The transfer characteristics of the luminance interpolation
filter are illustrated in Figs 7 and 8. Appropriate transients
at start/end of active video and for synchronization pulses
are ensured.
Chrominance is modified in gain (programmable
separately for C
burst is inserted, before baseband colour signals are
interpolated from a 6.75 MHz data rate to a 27 MHz data
rate. One of the interpolation stages can be bypassed,
thus providing a higher colour bandwidth, which can be
used for the Y and C output. The transfer characteristics of
the chrominance interpolation filter are illustrated in
Figs 5 and 6.
The amplitude (beginning and ending) of the inserted
burst, is programmable in a certain range that is suitable
for standard signals and for special effects. After the
succeeding quadrature modulator, colour is provided on
the subcarrier in 10-bit resolution.
The numeric ratio between the Y and C outputs is in
accordance with the standards.
8.12.2
Pin TTX_SRES receives a WST or NABTS teletext
bitstream sampled at the crystal clock. At each rising edge
of the output signal (TTXRQ) a single teletext bit has to be
provided after a programmable delay at input pin
TTX_SRES.
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
TTXRQ_XCLKO2 provides a fully programmable request
signal to the teletext source, indicating the insertion period
of bitstream at lines which can be selected independently
for both fields. The internal insertion window for text is set
to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.51.
Alternatively, this pin can be provided with a buffered
crystal clock (XCLK) of 13.5 MHz.
2004 Jun 29
HD-CODEC
T
SIMULTANEOUSLY WITH REAL
ELETEXT INSERTION AND ENCODING
B
and C
R
), and a standard dependent
-
TIME CONTROL
(
NOT
)
22
8.12.3
Five bytes of VPS information can be loaded via the
I
line 16.
8.12.4
Using this circuit, data in accordance with the specification
of Closed Caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.
The actual line number in which data is to be encoded, can
be modified in a certain range.
The data clock frequency is in accordance with the
definition for NTSC M standard 32 times horizontal line
frequency.
Data LOW at the output of the DACs corresponds to 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
It is also possible to encode Closed Caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.
8.12.5
For more information contact your nearest Philips
Semiconductors sales office.
8.13
This block contains a dematrix in order to produce RED,
GREEN and BLUE signals to be fed to a SCART plug.
Before Y, C
gain adjustment for Y and colour difference signals and
2 times oversampling for luminance and 4 times
oversampling for colour difference signals is performed.
The transfer curves of luminance and colour difference
components of RGB are illustrated in Figs 9 and 10.
8.14
Both Y and C signals are converted from digital-to-analog
in a 10-bit resolution at the output of the video encoder.
Y and C signals are also combined into a 10-bit CVBS
signal.
The CVBS output signal occurs with the same processing
delay as the Y, C and optional RGB or C
Absolute amplitude at the input of the DAC for CVBS is
reduced by
maximum use of the conversion ranges.
2
C-bus and will be encoded in the appropriate format into
RGB processor
Triple DAC
V
C
A
IDEO
NTI
LOSED
B
15
and C
-
16
TAPING
SAA7108AE; SAA7109AE
P
with respect to Y and C DACs to make
ROGRAMMING
C
APTION ENCODER
R
(SAA7108AE
signals are de-matrixed, individual
S
YSTEM
ONLY
Product specification
(VPS)
)
R
-Y-C
ENCODING
B
outputs.