SAA7108AE PHILIPS [NXP Semiconductors], SAA7108AE Datasheet - Page 23

• Manufacturer Part Number: SAA7108AE
• Description: HD-CODEC
• Manufacturer: PHILIPS [NXP Semiconductors]

Philips Semiconductors
RED, GREEN and BLUE signals are also converted from
digital-to-analog, each providing a 10-bit resolution.
The reference currents of all three DACs can be adjusted
individually in order to adapt for different output signals.
In addition, all reference currents can be adjusted
commonly to compensate for small tolerances of the
on-chip band gap reference voltage.
Alternatively, all currents can be switched off to reduce
power dissipation.
All three outputs can be used to sense for an external load
(usually 75 ) during a pre-defined output. A flag in the
I
not. An automatic sense mode can also be activated,
which will immediately indicate any 75
three outputs at the dedicated interrupt pin TVD.
If the SAA7108AE; SAA7109AE is required to drive a
second (auxiliary) VGA monitor or an HDTV set, the DACs
receive the signal coming from the HD data path. In this
event, the DACs are clocked at the incoming PIXCLKI
instead of the 27 MHz crystal clock used in the video
encoder.
8.15
This data path enables the SAA7108AE; SAA7109AE to
be used with VGA or HDTV monitors. It receives its data
directly from the cursor generator and supports RGB and
Y-P
formats). No scaling is done in this mode.
A gain adjustment either leads the full level swing to the
digital-to-analog converters or reduces the amplitude by a
factor of 0.69. This enables sync pulses to be added to the
signal as it is required for display units that require signals
with sync pulses, either regular or 3-level syncs.
8.16
The synchronization of the SAA7108AE; SAA7109AE is
able to operate in two modes; slave mode and master
mode.
In slave mode, the circuit accepts sync pulses on the
bidirectional FSVGC (frame sync), VSVGC (vertical sync)
and HSVGC (horizontal sync) pins: the polarities of the
signals can be programmed. The frame sync signal is only
necessary when the input signal is interlaced, in other
cases it may be omitted. If the frame sync signal is present,
it is possible to derive the vertical and the horizontal phase
from it by setting the HFS and VFS bits. HSVGC and
VSVGC are not necessary in this case, so it is possible to
switch the pins to output mode.
2004 Jun 29
2
C-bus status byte reflects whether a load is applied or
HD-CODEC
B
-P
HD data path
Timing generator
R
output formats (RGB not with Y-P
load at any of the
B
-P
R
input
23
Alternatively, the device can be triggered by auxiliary
codes in a ITU-R BT.656 data stream via PD7 to PD0.
Only vertical frequencies of 50 and 60 Hz are allowed with
the SAA7108AE; SAA7109AE. In slave mode, it is not
possible to lock the encoders colour carrier to the line
frequency with the PHRES bits.
In the (more common) master mode, the time base of the
circuit is continuously free-running. The IC can output a
frame sync at pin FSVGC, a vertical sync at pin VSVGC, a
horizontal sync at pin HSVGC and a composite blanking
signal at pin CBO. All of these signals are defined in the
PIXCLK domain. The duration of HSVGC and VSVGC are
fixed, they are 64 clocks for HSVGC and 1 line for VSVGC.
The leading slopes are in phase and the polarities can be
programmed.
The input line length can be programmed. The field length
is always derived from the field length of the encoder and
the pixel clock frequency that is being used.
CBO acts as a data request signal. The circuit accepts
input data at a programmable number of clocks after CBO
goes active. This signal is programmable and it is possible
to adjust the following (see Figs 49 and 50):
In most cases, the vertical offsets for odd and even fields
are equal. If they are not, then the even field will start later.
The SAA7108AE; SAA7109AE will also request the first
input lines in the even field, the total number of requested
lines will increase by the difference of the offsets.
As stated above, the circuit can be programmed to accept
the look-up and cursor data in the first 2 lines of each field.
The timing generator provides normal data request pulses
for these lines; the duration is the same as for regular lines.
The additional request pulses will be suppressed with
LUTL set to logic 0; see Table 143. The other vertical
timings do not change in this case, so the first active line
can be number 2, counted from 0.
The horizontal offset
The length of the active part of the line
The distance from active start to first expected data
The vertical offset separately for odd and even fields
The number of lines per input field.
SAA7108AE; SAA7109AE
Product specification