ADMC326TR AD [Analog Devices], ADMC326TR Datasheet - Page 11

• Manufacturer Part Number: ADMC326TR
• Description: 28-Lead ROM-Based DSP Motor Controller
• Manufacturer: AD [Analog Devices]

state. Because this hardware shutdown mechanism is asynchro-
nous, and the associated PWM disable circuitry does not use
clocked logic, the PWM will shut down even if the DSP clock is
not running. The PWM system may also be shut down from
software by writing to the PWMSWT register.
Status information about the PWM system of the ADMC326 is
available to the user in the SYSSTAT register. In particular, the
state of PWMTRIP is available, as well as a status bit that indi-
cates whether operation is in the first half or the second half of
the PWM period.
A functional block diagram of the PWM controller is shown in
Figure 6. The generation of the six output PWM signals on pins
AH to CL is controlled by four important blocks:
• The three-phase PWM timing unit, which is the core of the
• The output control unit allows the redirection of the outputs
• The GATE drive unit provides the high chopping frequency
• The PWM shutdown controller manages the three PWM
• The PWM controller is driven by a clock at the same frequency
REV. A
PWM controller, generates three pairs of complemented and
dead-time-adjusted center-based PWM signals.
of the three-phase timing unit for each channel to either the
high side or the low side output. In addition, the output con-
trol unit allows individual enabling/disabling of each of the six
PWM output signals.
and its subsequent mixing with the PWM signals.
shutdown modes (via the PWMTRIP pin, the analog block or
the PWMSWT register) and generates the correct RESET signal
for the Timing Unit.
as the DSP instruction rate, CLKOUT, and is capable of
generating two interrupts to the DSP core. One interrupt is
generated on the occurrence of a PWMSYNC pulse, and the
other is generated on the occurrence of any PWM shutdown
action.
PWM CONFIGURATION
PWMTM (15...0)
PWMDT (9...0)
PWMPD (15...0)
PWMSYNCWT (7...0)
MODECTRL (6)
TO INTERRUPT
CONTROLLER
REGISTERS
PWMSYNC
PWMTRIP
CLK
THREE-PHASE
PWM TIMING
SYNC
UNIT
PWM DUTY CYCLE
Figure 6. Overview of the PWM Controller of the ADMC326
PWMCHA (15...0)
PWMCHB (15...0)
PWMCHC (15...0)
RESET
REGISTERS
PWM SHUTDOWN CONTROLLER
–11–
Three-Phase Timing Unit
The 16-bit three-phase timing unit is the core of the PWM con-
troller and produces three pairs of pulsewidth modulated signals
with high resolution and minimal processor overhead. There are
four main configuration registers (PWMTM, PWMDT, PWMPD
and PWMSYNCWT) that determine the fundamental charac-
teristics of the PWM outputs. In addition, the operating mode
of the PWM (single or double update mode) is selected by Bit 6
of the MODECTRL register. These registers, in conjunction with
the three 16-bit duty cycle registers (PWMCHA, PWMCHB and
PWMCHC), control the output of the three-phase timing unit.
PWM Switching Frequency: PWMTM Register
The PWM switching frequency is controlled by the PWM
period register, PWMTM. The fundamental timing unit of
the PWM controller is t
CLKOUT frequency (DSP instruction rate). Therefore, for a
20 MHz CLKOUT, the fundamental time increment is 50 ns.
The value written to the PWMTM register is effectively the
number of t
required PWMTM value is a function of the desired PWM
switching frequency (f
Therefore, the PWM switching period, T
For example, for a 20 MHz CLKOUT and a desired PWM
switching frequency of 10 kHz (T
to load into the PWMTM register is:
OR
PWMSEG (8...0)
CONTROL
OUTPUT
SYNC
UNIT
PWMSWT (0)
PWMTM
CK
clock increments in half a PWM period. The
PWMTM
T
S
PWMGATE (9...0)
PWM
CK
2
2
DRIVE
GATE
UNIT
CLK
) and is given by:
20
= 1/f
10
PWMTM
2
f
CLKOUT
10
CLKOUT
S
f
10
6
PWM
= 100 s), the correct value
CLKOUT
3
1000
where f
S
, can be written as:
t
f
CK
AH
AL
BL
CL
f
BH
CH
CLKIN
PWMTRIP
PWM
ADMC326
0 3 8
x E
CLKOUT
is the