ADMC326TR AD [Analog Devices], ADMC326TR Datasheet - Page 21

• Manufacturer Part Number: ADMC326TR
• Description: 28-Lead ROM-Based DSP Motor Controller
• Manufacturer: AD [Analog Devices]

SYSTEM CONTROLLER
The system controller block of the ADMC326 performs the fol-
lowing functions:
1. Manages the interface and data transfer between the DSP
2. Handles interrupts generated by the motor control periph-
3. Controls the ADC multiplexer select lines.
4. Enables PWMTRIP and PWMSYNC interrupts.
5. Controls the multiplexing of the SPORT1 pins to select
6. Controls the PWM single/double update mode.
7. Controls the ADC conversion time modes.
8. Controls the auxiliary PWM operation mode.
9. Contains a status register (SYSSTAT) that indicates the
10. Performs a reset of the motor control peripherals and con-
SPORT1 Control
Both data receive pins are multiplexed internally into the single
data receive input of SPORT1 as shown in Figure 18. Two
control bits in the MODECTRL register control the state of
the SPORT1 pins by manipulating internal multiplexers in
the ADMC326.
REV. A
core and the motor control peripherals.
erals and generates a DSP core interrupt signal IRQ2.
either DR1A or DR1B data receive pins. It also allows con-
figuration of SPORT1 as a UART interface.
state of the PWMTRIP pin, the watchdog timer and the
PWM timer.
trol registers following a hardware, software or watchdog
initiated reset.
DSP
CORE
SPORT1
Figure 18. Internal Multiplexing of SPORT1 Pins
SCLK1
RFS1
TFS1
DR1
DT1
FL1
MODECTRL (5 . . . 4)
ADMC326
UARTEN
DR1SEL
PIO1/DT1
PIO2/DR1B
PIO4/DR1A
PIO0/TFS1
PIO5/RFS1
PIO3/SCLK1
–21–
Bit 4 of the MODECTRL register (DR1SEL) selects between
the two data receive pins. Setting Bit 4 of MODECTRL con-
nects pin DR1B to the internal data receive port DR1 of SPORT1.
Clearing Bit 4 connects DR1A to DR1.
Setting Bit 5 of the MODECTRL register (SPORT1 Mode)
configures the serial port for UART mode. In this mode, the
DR1 and RFS1 pins of the internal serial port are connected to-
gether. Additionally, setting the SPORT1 Mode bit connects
the FL1 flag of the DSP to the external PIO5/RFS1 pin.
Flag Pins
The ADMC326 provides flag pins. The alternate configuration
of SPORT1 includes a Flag In (FI) and Flag Out (FO) pin.
This alternate configuration of SPORT1 is selected by Bit 10 of
the DSP system control register, SYSCNTL at data memory
address, 0x3FFF. In the alternate configuration, the DR1 pin
(either DR1A or DR1B depending upon the state of the DR1SEL
bit) becomes the FI pin and the DT1 pin becomes the FO pin.
Additionally, RFS1 is configured as the IRQ0 interrupt input
and TFS1 is configured as the IRQ1 interrupt. The serial port
clock, SCLK1, is still available in the alternate configuration.
Development Tools
Users are recommended to obtain the ADMCF326-EVALKIT
from Analog Devices. The tool kit contains everything required
to quickly and easily evaluate and develop applications using the
ADMCF326 and ADMC326 DSP Motor Controllers. Please
contact your ADI sales representative for ordering information.
ADMC326