ADMC326TR AD [Analog Devices], ADMC326TR Datasheet - Page 29

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ADMC326TR

Manufacturer Part Number
ADMC326TR
Description
28-Lead ROM-Based DSP Motor Controller
Manufacturer
AD [Analog Devices]
Datasheet
REV. A
Default bit values are shown; if no value is shown, the bit field is undefined at reset. Reserved bits are shown on a gray field—these
bits should always be written as shown.
1 = INDEPENDENT MODE
1 = CLKOUT RATE
0 = OFFSET MODE
0 = CLKIN RATE
0 = 1ST HALF OF PWM
1 = 2ND HALF OF PWM
CYCLE
CYCLE
15
15
15
0
0
0
14
14
14
0
0
0
PWM SELECT
AUXILIARY
COUNTER
15
SELECT
0
13
13
13
0
0
0
ADC
14
0
12
12
12
0
0
0
13
PWM TIMER
0
11
11
11
0
Figure 25. Configuration of Status Registers
STATUS
0
0
12
0
10
10
10
0
0
0
11
0
9
0
0
9
WDTIMER (W)
9
0
SYSSTAT (R)
IRQFLAG (R)
10
0
8
8
0
8
0
0
MODECTRL (R/W)
0
9
0
7
0
7
7
0
8
0
6
0
6
0
6
0
7
0
–29–
5
0
5
0
5
0
6
0
0
0
4
0
4
4
5
0
0
3
3
0
3
0
4
2
1
2
0
2
0
3
0
0
1
1
1
0
2
0
0
0
0
0
0
1
0
WATCHDOG
PIN STATUS
DM (0x2016)
PWMTRIP INTERRUPT
PWMSYNC INTERRUPT
DM (0x2018)
PWMTRIP
SPORT1 MODE
DM (0x2017)
SPORT1 DATA
MODE SELECT
STATUS
PWM UPDATE
INTERRUPT
INTERRUPT
PWMSYNC
PWMTRIP
0
0
RECEIVE
SELECT
SELECT
DM (0x2015)
ADC MUX CONTROL
00 VAUX0
01 VAUX1
10 VAUX2
11 VAUX3
0 = LOW
1 = HIGH
0 = NORMAL
1 = WATCHDOG RESET
0 = DISABLE
1 = ENABLE
0 = DISABLE
1 = ENABLE
0 = DR1A
1 = DR1B
0 = SPORT
1 = UART
0 = SINGLE UPDATE MODE
1 = DOUBLE UPDATE MODE
OCCURRED
0 = NO INTERRUPT
1 = INTERRUPT
OCCURRED
ADMC326

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