ADMC326TR AD [Analog Devices], ADMC326TR Datasheet - Page 14

• Manufacturer Part Number: ADMC326TR
• Description: 28-Lead ROM-Based DSP Motor Controller
• Manufacturer: AD [Analog Devices]

after the PWMCHA, PWMCHB, and PWMCHC registers,
then the first PWMSYNC pulse (and interrupt if enabled) will
be generated (1.5
write to the PWMTM register in single update mode. In double
update mode, the first PWMSYNC pulse will be generated
(t
register in single update mode.
Effective PWM Resolution
In single update mode, the same values of PWMCHA, PWMCHB
and PWMCHC are used to define the on-times in both half
cycles of the PWM period. As a result, the effective resolution of
the PWM generation process is 2 t
CLKOUT) since incrementing one of the duty cycle registers by
one changes the resultant on-time of the associated PWM sig-
nals by t
In double update mode, improved resolution is possible since
different values of the duty cycles registers are used to define the
on-times in both the first and second halves of the PWM period.
As a result, it is possible to adjust the on-time over the whole
period in increments of t
PWM resolution of t
20 MHz CLKOUT).
The achievable PWM switching frequency at a given PWM
resolution is tabulated in Table IV.
Table IV. Achievable PWM Resolution in Single and Double
Update Modes
Resolution
(Bit)
8
9
10
11
12
Minimum Pulsewidth: PWMPD Register
In many power converter switching applications, it is desirable
to eliminate PWM switching pulses shorter than a certain width.
It takes a finite time to both turn on and turn off modern power
semiconductor devices. Therefore, if the width of any of the PWM
pulses is shorter than some minimum value, it may be desirable to
completely eliminate the PWM switching for that particular cycle.
The allowable minimum on-time for any of the six PWM out-
puts for half a PWM period that can be produced by the PWM
controller may be programmed using the PWMPD register. The
minimum on-time is programmed in increments of t
the minimum on-time that will be produced for any half PWM
period, T
A PWMPD value of 0x002 defines a permissible minimum
on-time of 100 ns for a 20 MHz CLKOUT.
In each half cycle of the PWM, the timing unit checks the on-
time of each of the six PWM signals. If any of the times is found
to be less than the value specified by the PWMPD register, the
corresponding PWM signal is turned OFF for the entire half
period, and its complementary signal is turned completely ON.
Consider the example where PWMTM = 200, PWMCHA = 5,
PWMDT = 3, and PWMPD = 10 with a CLKOUT of 20 MHz
ADMC326
CK
PWMTM) seconds after the initial write to the PWMTM
CK
MIN
in each half period (or 2 t
, is related to the value in the PWMPD register by:
Single Update Mode
PWM Frequency (kHz)
39.1
19.5
9.8
4.9
2.4
CK
t
T
CK
MIN
in double update mode (or 50 ns for a
CK
= PWMPD t
PWMTM) seconds after the initial
. This corresponds to an effective
CK
CK
(or 100 ns for a 20 MHz
for the full period).
Double Update Mode
PWM Frequency (kHz)
78.1
39.1
19.5
9.8
4.9
CK
CK
so that
–14–
while operating in single update mode. For this case, the PWM
switching frequency is 50 kHz and the dead time is 300 ns. The
minimum permissible on-time of any PWM signal over one-half
of any period is 500 ns. Clearly, for this example, the dead-time
adjusted on-time of the AH signal for one-half a PWM period is
(5–3) 50 ns = 100 ns. Because this is less than the minimum
permissible value, output AH of the timing unit will remain
OFF (0% duty cycle). Additionally, the AL signal will be turned
ON for the entire half period (100% duty cycle).
Output Control Unit: PWMSEG Register
The operation of the output control unit is managed by the 9-bit
read/write PWMSEG register. This register sets two distinct
features of the output control unit that are directly useful in the
control of ECM or BDCM.
The PWMSEG register contains three crossover bits, one for each
pair of PWM outputs. Setting Bit 8 of the PWMSEG register
enables the crossover mode for the AH/AL pair of PWM signals;
setting Bit 7 enables crossover on the BH/BL pair of PWM signals;
and setting Bit 6 enables crossover on the CH/CL pair of PWM
signals. If crossover mode is enabled for any pair of PWM signals,
the high-side PWM signal from the timing unit (for example
AH) is diverted to the associated low-side output of the output
control unit so that the signal will ultimately appear at the AL
pin. Of course, the corresponding low-side output of the timing
unit is also diverted to the complementary high-side output of
the output control unit so that the signal appears at Pin AH.
Following a reset, the three crossover bits are cleared so that the
crossover mode is disabled on all three pairs of PWM signals.
The PWMSEG register also contains six bits (Bits 0 to 5) that
can be used to individually enable or disable each of the six PWM
outputs. If the associated bit of the PWMSEG register is set,
the corresponding PWM output is disabled regardless of the
value of the corresponding duty cycle register. This PWM output
signal will remain in the OFF state as long as the corresponding
enable/disable bit of the PWMSEG register is set. The PWM
output enable function gates the crossover function. After a
reset, all six enable bits of the PWMSEG register are cleared,
thereby enabling all PWM outputs by default.
In a manner identical to the duty cycle registers, the PWMSEG is
latched on the rising edge of the PWMSYNC signal so that changes
to this register only become effective at the start of each PWM
cycle in single update mode. In double update mode, the PWM-
SEG register can also be updated at the midpoint of the PWM cycle.
In the control of an ECM, only two inverter legs are switched
at any time, and often the high-side device in one leg must be
switched ON at the same time as the low-side driver in a second
leg. Therefore, by programming identical duty cycles for two PWM
channels (for example, let PWMCHA = PWMCHB) and setting
Bit 7 of the PWMSEG register to crossover the BH/BL pair of
PWM signals, it is possible to turn ON the high-side switch of
Phase A and the low-side switch of Phase B at the same time. In
the control of an ECM, one inverter leg (Phase C in this example)
is disabled for a number of PWM cycles. This disable may be
implemented by disabling both the CH and CL PWM outputs
by setting Bits 0 and 1 of the PWMSEG register. This is illus-
trated in Figure 9 where it can be seen that both the AH and
BL signals are identical, because PWMCHA = PWMCHB, and
the crossover bit for Phase B is set. In addition, the other four
signals (AL, BH, CH, and CL) have been disabled by setting
the appropriate enable/disable bits of the PWMSEG register.
REV. A