ADMC326TR AD [Analog Devices], ADMC326TR Datasheet - Page 13

• Manufacturer Part Number: ADMC326TR
• Description: 28-Lead ROM-Based DSP Motor Controller
• Manufacturer: AD [Analog Devices]

The PWM is center-based. This means that in single update mode
the resulting output waveforms are symmetrical and centered in
the PWMSYNC period. Figure 7 presents a typical PWM tim-
ing diagram illustrating the PWM-related registers’ (PWMCHA,
PWMTM, PWMDT, and PWMSYNCWT) control over the
waveform timing in both half cycles of the PWM period. The
magnitude of each parameter in the timing diagram is determined
by multiplying the integer value in each register by t
50 ns). It may be seen in the timing diagram how dead time is
incorporated into the waveforms by moving the switching edges
away from the instants set by the PWMCHA register.
Each switching edge is moved by an equal amount (PWMDT
pulse, whose width is set by the PWMSYNCWT register, is also
shown. Bit 3 of the SYSSTAT register indicates which half cycle
is active. This can be useful in double update mode, as will be
discussed later.
The resultant on-times of the PWM signals shown in Figure 7
may be written as:
The corresponding duty cycles are:
Obviously, negative values of T
because the minimum permissible value is zero, corresponding
to a 0% duty cycle. In a similar fashion, the maximum value is
T
REV. A
The output signals from the timing unit for operation in double
update mode are shown in Figure 8. This illustrates a completely
general case where the switching frequency, dead time and duty
cycle are all changed in the second half of the PWM period. Of
course, the same value for any or all of these quantities could be
used in both halves of the PWM cycle. However, it can be seen
that there is no guarantee that symmetrical PWM signals will be
produced by the timing unit in this double update mode. Addi-
tionally, it is seen that the dead time is inserted into the PWM
signals in the same way as in the single update mode.
SYSSTAT (3)
S
Figure 7. Typical PWM Outputs of Three-Phase Timing
Unit in Single Update Mode
t
PWMSYNC
CK
, corresponding to a 100% duty cycle.
T
T
) to preserve the symmetrical output patterns. The PWMSYNC
AH
AL
d
d
AH
AL
AH
AL
2
2
2
T
T
T
T
AL
(
AH
(
S
S
PWMTM
PWMDT
PWMCHA
PWMTM
PWMTM
PWMCHA
–
PWMCHA
PWMTM
–
PWMCHA
PWMDT
–
AH
–
PWMCHA
PWMTM
PWMDT
and T
PWMCHA
)
–
AL
PWMDT
t
PWMSYNCWT + 1
are not permitted
CK
PWMTM
–
PWMDT
2
CK
PWMDT
)
(typically
t
CK
–13–
In general, the on-times of the PWM signals in double update
mode are defined by:
where the subscript 1 refers to the value of that register during
the first half cycle and the subscript 2 refers to the value during
the second half cycle. The corresponding duty cycles are:
because for the completely general case in double update mode,
the switching period is given by:
Again, the values of T
zero and T
PWM signals similar to those illustrated in Figure 7 and Figure
8 can be produced on the BH, BL, CH, and CL outputs by pro-
gramming the PWMCHB and PWMCHC registers in a manner
identical to that described for PWMCHA.
The PWM controller does not produce any PWM outputs until
all of the PWMTM, PWMCHA, PWMCHB, and PWMCHC
registers have been written to at least once. After these registers
have been written, the counters in the three-phase timing unit
are enabled. Writing to these registers also starts the main PWM
timer. If during initialization, the PWMTM register is written
SYSSTAT (3)
Figure 8. Typical PWM Outputs of Three-Phase Timing
Unit in Double Update Mode
PWMSYNC
T
T
AH
AL
AH
AL
= (PWMTM
= (PWMCHA
d
d
– PWMCHA
S
AH
AL
– PWMDT
.
2
T
–
PWMDT
PWMSYNCWT
T
S
T
T
T
PWMTM
PWCHA
PWMCHA
PWMTM
= (PWMTM
AL
AH
PWMDT
S
PWMTM
PWMTM
S
1
1
AH
+ PWMTM
1
2
PWMTM
2
+ PWMCHA
)
1
– PWMDT
PWMTM
and T
PWMCHA
1
2
1
1
+ 1
1
t
CK
1
1
PWMDT
1
PWMDT
PWMTM
PWMTM
AL
PWMCHA
PWMTM
+ PWMTM
1
1
are constrained to lie between
2
1
PWMCHA
– PWMCHA
1
PWMTM
– PWMDT
2
PWMTM
– PWMDT
1
2
2
2
2
PWMDT
2
PWMTM
2
2
PWMCHA
PWMSYNCWT
)
ADMC326
2
t
2
2
1
CK
)
2
1
2
2
t
PWMDT
CK
2
1
+ 1
2