EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 37

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Figure 2–23. Global Clock Network Multiplexers
Altera Corporation
January 2007
Dual-Purpose Clocks [7..0]
Global Clocks [3..0]
PLL Outputs [3..0]
Core Logic [7..0]
Dual-Purpose Clock Pins
Each Cyclone device except the EP1C3 device has eight dual-purpose
clock pins, DPCLK[7..0] (two on each I/O bank). EP1C3 devices have
five DPCLK pins in the 100-pin TQFP package. These dual-purpose pins
can connect to the global clock network (see
control signals such as clocks, asynchronous clears, presets, and clock
enables, or protocol control signals such as TRDY and IRDY for PCI, or
DQS signals for external memory interfaces.
Combined Resources
Each Cyclone device contains eight distinct dedicated clocking resources.
The device uses multiplexers with these clocks to form six-bit buses to
drive LAB row clocks, column IOE clocks, or row IOE clocks. See
Figure
LAB row clocks to feed the LE registers within the LAB.
IOE clocks have row and column block regions. Six of the eight global
clock resources feed to these row and column regions.
the I/O clock regions.
2–23. Another multiplexer at the LAB level selects two of the six
Global Clock
Network
Clock [7..0]
Global Clock Network & Phase-Locked Loops
Figure
2–22) for high-fanout
Column I/O Region
IO_CLK]5..0]
LAB Row Clock [5..0]
Row I/O Region
IO_CLK[5..0]
Figure 2–24
Preliminary
shows
2–31