EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 49

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Figure 2–30. Signal Path through the I/O Block
Altera Corporation
January 2007
From Logic
To Logic
Array
Array
comb_io_datain
Row or Column
io_cce_out
io_clk[5..0]
io_dataout
io_cce_in
io_datain
io_csclr
io_caclr
io_cclk
io_coe
The pin's datain signals can drive the logic array. The logic array drives
the control and data signals, providing a flexible routing resource. The
row or column IOE clocks, io_clk[5..0], provide a dedicated routing
resource for low-skew, high-speed clocks. The global clock network
generates the IOE clocks that feed the row or column I/O regions (see
“Global Clock Network & Phase-Locked Loops” on page
Figure 2–30
Each IOE contains its own control signal selection for the following
control signals: oe, ce_in, ce_out, aclr/preset, sclr/preset,
clk_in, and clk_out.
selection.
Data and
Selection
Control
Signal
illustrates the signal paths through the I/O block.
oe
ce_in
ce_out
aclr/preset
sclr
clk_in
clk_out
dataout
Figure 2–31
To Other
IOEs
illustrates the control signal
IOE
2–29).
I/O Structure
Preliminary
2–43