EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 55

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Figure 2–34. DDR SDRAM & FCRAM Interfacing
Altera Corporation
January 2007
PLL
OE
Phase Shifted -90˚
Register
OE LE
Register
OE LE
GND
V
CC
Output LE
Output LE
Register
Register
Programmable Drive Strength
The output buffer for each Cyclone device I/O pin has a programmable
drive strength control for certain I/O standards. The LVTTL and
LVCMOS standards have several levels of drive strength that the designer
can control. SSTL-3 class I and II, and SSTL-2 class I and II support a
minimum setting, the lowest drive strength that guarantees the I
Programmable
Delay Chain
clk
DQS
Δ t
OE
Register
OE LE
Global Clock
Register
OE LE
DataA
DataB
Output LE
Output LE
Registers
Registers
-90˚ clk
DQ
Adjacent LAB LEs
Register
Register
LE
LE
Registers
Registers
Input LE
Input LE
I/O Structure
Preliminary
Adjacent
LAB LEs
Resynchronizing
Global Clock
OH
/I
2–49
OL