EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet - Page 53

• Manufacturer Part Number: EP1C4
• Description: Cyclone FPGA Family Data Sheet
• Manufacturer: ALTERA [Altera Corporation]

Figure 2–33. Cyclone Device DQ & DQS Groups in × 8 Mode
Note to
(1)
Altera Corporation
January 2007
Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin.
Figure
Top, Bottom, Left, or Right I/O Bank
2–33:
output pins (nSTATUS and CONF_DONE) and all the JTAG pins in I/O
bank 3 must operate at 2.5 V because the V
I/O banks 1, 2, 3, and 4 support DQS signals with DQ bus modes of × 8.
For × 8 mode, there are up to eight groups of programmable DQS and DQ
pins, I/O banks 1, 2, 3, and 4 each have two groups in the 324-pin and
400-pin FineLine BGA packages. Each group consists of one DQS pin, a
set of eight DQ pins, and one DM pin (see
drives the set of eight DQ pins within that group.
Table 2–10
EP1C3
EP1C4
Table 2–10. DQ Pin Groups (Part 1 of 2)
Device
DQ Pins
shows the number of DQ pin groups per device.
100-pin TQFP
324-pin FineLine BGA
144-pin TQFP
400-pin FineLine BGA
DQS Pin
Package
(1)
Note (1)
Number of × 8 DQ
Pin Groups
Figure
CCIO
3
4
8
8
level of SSTL-2 is 2.5 V.
2–33). Each DQS pin
DM Pin
Total DQ Pin
I/O Structure
Count
Preliminary
24
32
64
64
2–47