MK60N256VLL100 FREESCALE [Freescale Semiconductor, Inc], MK60N256VLL100 Datasheet - Page 59

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MK60N256VLL100

Manufacturer Part Number
MK60N256VLL100
Description
Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
6.8.7 DSPI switching specifications (high-speed mode)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The tables
below provide DSPI timing characteristics for classic SPI timing modes. Refer to the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Freescale Semiconductor, Inc.
DS10
DS11
DS12
DS13
DS14
DS15
DS16
Num
Num
DS9
DSPI_SS
DSPI_SCK
(CPOL=0)
DSPI_SOUT
DSPI_SIN
Operating voltage
Frequency of operation
DSPI_SCK input cycle time
DSPI_SCK input high/low time
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSIP_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
Operating voltage
Frequency of operation
Table 41. Master mode DSPI timing (high-speed mode)
Table 40. Slave mode DSPI timing (low-speed mode)
Figure 25. DSPI classic SPI timing — slave mode
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
DS13
DS15
Description
Description
Table continues on the next page...
First data
First data
DS14
Preliminary
DS10
DS12
Data
Data
Peripheral operating requirements and behaviors
(t
DS11
8 x t
SCK
1.71
Min.
Min.
2.7
15
DS9
0
5
/2) - 4
BCLK
Last data
Last data
DS16
(t
SCK/2)
Max.
Max.
6.25
3.6
3.6
20
15
15
25
+ 4
MHz
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
V
59

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