MK60N256VLL100 FREESCALE [Freescale Semiconductor, Inc], MK60N256VLL100 Datasheet - Page 63

• Manufacturer Part Number: MK60N256VLL100
• Description: Up to 100 MHz ARM Cortex-M4 core with DSP instructions delivering 1.25 Dhrystone MIPS per MHz
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor, Inc.
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
I2S_RXD
Num
Num
S10
S11
S12
S13
S14
S15
S16
S17
S2
S3
S4
S5
S6
S7
S8
S9
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
I2S_BCLK to I2S_TXD valid
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
Operating voltage
I2S_BCLK cycle time (input)
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
Description
Description
S5
S7
Table 44. I
K60 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.
S4
Figure 29. I
S9
Table 45. I
S9
S1
Table continues on the next page...
2
S3
S master mode timing (continued)
S2
S10
2
S timing — master mode
2
Preliminary
S slave mode timing
S4
S2
S8
S7
Peripheral operating requirements and behaviors
5 x t
8 x t
45%
45%
45%
Min.
Min.
-2.5
2.7
20
10
10
—
—
—
-3
0
3
0
SYS
SYS
Max.
55%
55%
Max.
55%
3.6
15
15
20
—
—
—
—
—
—
—
—
—
—
MCLK period
MCLK period
S10
BCLK period
S6
S8
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
63