KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 31

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

March 2010
Micrel, Inc.
Write an “1” to RXQCR[3] reg to enable
Write an “1” to TXQCR[0] reg to issue a
that the TXQ has completed to transmit
to KSZ8851M TXQ memory until whole
Option to Read ISR[14] reg, it indicates
This is moving transmit data from Host
upper layer and prepares transmit pkt
to the TXQ. The TXQ will transmit this
write transmit data (control word, byte
transmit command (manual-enqueue)
at least one pkt to the PHY port, then
count and pkt data) to TXQ memory.
Write an “0” to RXQCR[3] reg to end
data (data, data_length, frame ID).
The transmit queue frame format is
Host receives an Ethernet pkt from
TXQ write access, then Host starts
Figure 7. Host TX Single Frame in Manual Enqueue Flow Diagram
Memory size is available for this
Check if KSZ8851M TXQ
pkt data to the PHY port
Write “1” to clear this bit
(Read TXMIR Reg)
shown in Table 5
TXQ write access
pkt is finished
transmit pkt?
Yes
31
No
Yes
Write the total amount of TXQ buffer
transmit frame size in double-word
enable the TXQ memory available
count in TXNTFSR[15:0] register
Set bit 1=1 in TXQCR register to
space which is required for next
(memory space available)
and check if the bit 6=1
Wait for interrupt
in ISR register
monitor
?
M9999-030210-1.0
KSZ8851-16MLLJ
No