KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 64

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Interrupt Enable Register (0x90 – 0x91): IER (Continued)
Interrupt Status Register (0x92 – 0x93): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register
bits are not cleared when read. The user has to write “1” to clear.
March 2010
Micrel, Inc.
Bit
2
1
0
Bit
15
14
13
12
11
10
9
8
7
6
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x1
0x1
0x0
0x0
Default Value
Default Value
R/W
RW
RO
RW
R/W
RO
(W1C)
RO
(W1C)
RO
(W1C)
RO
RO
(W1C)
RO
RO
(W1C)
RO
(W1C)
RO
RO
(W1C)
Description
EDIE Energy Detect Interrupt Enable
When this bit is set, the wake-up from energy detect interrupt is enabled.
When this bit is reset, the energy detect interrupt is disabled.
Reserved.
DEDIE Delay Energy Detect Interrupt Enable
When this bit is set, the delay energy detect interrupt is enabled.
When this bit is reset, the delay energy detect interrupt is disabled.
Note: the delay energy detect interrupt till device is ready for host access.
Description
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link down,
or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXIS Transmit Interrupt Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on the
MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received at least a frame from the
MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
TXPSIS Transmit Process Stopped Interrupt Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXPSIS Receive Process Stopped Interrupt Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
TXSAIS Transmit Space Available Interrupt Status
When this bit is set, it indicates that Transmit memory space available status has occurred.
When this bit is reset, the Transmit memory space available interrupt is disabled.
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M9999-030210-1.0
KSZ8851-16MLLJ