KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 32

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

March 2010
Micrel, Inc.
Host receives an multiple Ethernet pkts
from upper layer and prepares transmit
Write an “1” to RXQCR[3] reg to enable
that the TXQ has completed to transmit
ID). Each transmit queue frame format
This is moving transmit data from Host
Option to read ISR[14] reg, it indicates
write transmit data (control word, byte
count and pkt data) to TXQ memory.
Write an “0” to RXQCR[3] reg to end
pkts data (data, data_length, frame
to issue a transmit command (auto-
enqueue) to the TXQ. The TXQ will
to KSZ8851M TXQ memory until all
TXQ write access, then Host starts
Memory size is available for these
transmit all data to the PHY port
Write an “1” to TXQCR[2] reg
all pkts to the PHY port, then
Figure 8. Host TX Multiple Frames in Auto- Enqueue Flow Diagram
Check if KSZ8851M TXQ
Write “1” to clear this bit
is shown in Table 5
(Read TXMIR Reg)
TXQ write access
pkts are finished
transmit pkts?
Yes
32
No
Yes
word count in TXNTFSR[15:0] register
Write the total amount of TXQ buffer
transmit total frames size in double-
enable the TXQ memory available
Set bit 1=1 in TXQCR register to
space which is required for next
(memory space available)
and check if the bit 6=1
Wait for interrupt
in ISR register
monitor
?
M9999-030210-1.0
KSZ8851-16MLLJ
No