KSZ8851-16MLLJ_10 MICREL [Micrel Semiconductor], KSZ8851-16MLLJ_10 Datasheet - Page 6

• Manufacturer Part Number: KSZ8851-16MLLJ_10
• Description: Single-Port Ethernet MAC Controller with 8-Bit or 16-Bit Non-PCI Interface
• Manufacturer: MICREL [Micrel Semiconductor]

Micrel, Inc.
KSZ8851-16MLLJ
Host MAC Address Register Middle (0x12 – 0x13): MARM......................................................................................... 46
Host MAC Address Register High (0x14 – 0x15): MARH ............................................................................................ 46
On-Chip Bus Control Register (0x20 – 0x21): OBCR .................................................................................................. 47
EEPROM Control Register (0x22 – 0x23): EEPCR ..................................................................................................... 47
Memory BIST Info Register (0x24 – 0x25): MBIR ........................................................................................................ 48
Global Reset Register (0x26 – 0x27): GRR ................................................................................................................. 48
Wakeup Frame Control Register (0x2A – 0x2B): WFCR ............................................................................................. 49
Wakeup Frame 0 CRC0 Register (0x30 – 0x31): WF0CRC0 ...................................................................................... 49
Wakeup Frame 0 CRC1 Register (0x32 – 0x33): WF0CRC1 ...................................................................................... 50
Wakeup Frame 0 Byte Mask 0 Register (0x34 – 0x35): WF0BM0 .............................................................................. 50
Wakeup Frame 0 Byte Mask 1 Register (0x36 – 0x37): WF0BM1 .............................................................................. 50
Wakeup Frame 0 Byte Mask 2 Register (0x38 – 0x39): WF0BM2 .............................................................................. 50
Wakeup Frame 0 Byte Mask 3 Register (0x3A – 0x3B): WF0BM3.............................................................................. 50
Wakeup Frame 1 CRC0 Register (0x40 – 0x41): WF1CRC0 ...................................................................................... 51
Wakeup Frame 1 CRC1 Register (0x42 – 0x43): WF1CRC1 ...................................................................................... 51
Wakeup Frame 1 Byte Mask 0 Register (0x44 – 0x45): WF1BM0 .............................................................................. 51
Wakeup Frame 1 Byte Mask 1 Register (0x46 – 0x47): WF1BM1 .............................................................................. 51
Wakeup Frame 1 Byte Mask 2 Register (0x48 – 0x49): WF1BM2 .............................................................................. 51
Wakeup Frame 1 Byte Mask 3 Register (0x4A – 0x4B): WF1BM3.............................................................................. 52
Wakeup Frame 2 CRC0 Register (0x50 – 0x51): WF2CRC0 ...................................................................................... 52
Wakeup Frame 2 CRC1 Register (0x52 – 0x53): WF2CRC1 ...................................................................................... 52
Wakeup Frame 2 Byte Mask 0 Register (0x54 – 0x55): WF2BM0 .............................................................................. 52
Wakeup Frame 2 Byte Mask 1 Register (0x56 – 0x57): WF2BM1 .............................................................................. 52
Wakeup Frame 2 Byte Mask 2 Register (0x58 – 0x59): WF2BM2 .............................................................................. 53
Wakeup Frame 2 Byte Mask 3 Register (0x5A – 0x5B): WF2BM3.............................................................................. 53
Wakeup Frame 3 CRC0 Register (0x60 – 0x61): WF3CRC0 ...................................................................................... 53
Wakeup Frame 3 CRC1 Register (0x62 – 0x63): WF3CRC1 ...................................................................................... 53
Wakeup Frame 3 Byte Mask 0 Register (0x64 – 0x65): WF3BM0 .............................................................................. 53
Wakeup Frame 3 Byte Mask 1 Register (0x66 – 0x67): WF3BM1 .............................................................................. 54
Wakeup Frame 3 Byte Mask 2 Register (0x68 – 0x69): WF3BM2 .............................................................................. 54
Wakeup Frame 3 Byte Mask 3 Register (0x6A – 0x6B): WF3BM3.............................................................................. 54
Transmit Control Register (0x70 – 0x71): TXCR.......................................................................................................... 55
Transmit Status Register (0x72 – 0x73): TXSR ........................................................................................................... 56
Receive Control Register 1 (0x74 – 0x75): RXCR1 ..................................................................................................... 56
Receive Control Register 1 (0x74 – 0x75): RXCR1 (Continued) ................................................................................. 57
Receive Control Register 2 (0x76 – 0x77): RXCR2 ..................................................................................................... 57
TXQ Memory Information Register (0x78 – 0x79): TXMIR .......................................................................................... 58
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR ............................................................................. 58
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (Continued) ......................................................... 59
Receive Frame Header Status Register (0x7C – 0x7D): RXFHSR (Continued) ......................................................... 59
Receive Frame Header Byte Count Register (0x7E – 0x7F): RXFHBCR.................................................................... 59
TXQ Command Register (0x80 – 0x81): TXQCR ........................................................................................................ 59
RXQ Command Register (0x82 – 0x83): RXQCR........................................................................................................ 60
RXQ Command Register (0x82 – 0x83): RXQCR (Continued).................................................................................... 61
TX Frame Data Pointer Register (0x84 – 0x85): TXFDPR .......................................................................................... 61
RX Frame Data Pointer Register (0x86 – 0x87): RXFDPR.......................................................................................... 62
March 2010
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M9999-030210-1.0