KSZ8864RMNI MICREL [Micrel Semiconductor], KSZ8864RMNI Datasheet - Page 46

• Manufacturer Part Number: KSZ8864RMNI
• Description: Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces
• Manufacturer: MICREL [Micrel Semiconductor]

September 2011
MII Management Interface (MIIM)
The KSZ8864RMN supports the standard IEEE 802.3 MII Management Interface, also known as the Management
Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the
KSZ8864RMN. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY
settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification.
The MIIM interface consists of the following:



The MIIM Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 9 depicts the MII Management Interface frame format.
The MIIM interface does not have access to all the configuration registers in the KSZ8864RMN. It can only access
the standard MIIM registers. See “MIIM Registers”. The SPI interface and MDC/MDIO SMI mode, on the other hand,
can be used to access the entire KSZ8864RMN feature set.
Serial Management Interface (SMI)
The SMI is the KSZ8864RMN non-standard MIIM interface that provides access to all KSZ8864RMN configuration
registers. This interface allows an external device with MDC/MDIO interface to completely monitor and control the
states of the KSZ8864RMN.
The SMI interface consists of the following:
A physical connection that incorporates the data line (MDIO) and the clock line (MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external controller to
communicate with the KSZ8864RMN device.
Access all KSZ8864RMN configuration registers. Register access includes the Global, Port and Advanced Control
Registers 0-255 (0x00 – 0xFF), and indirect access to the standard MIIM registers [0:5] and custom MIIM registers
[29, 31].
The SMI Interface can operate up to a maximum clock speed of 10MHz MDC clock.
Table 10 depicts the SMI frame format.
Read
Write
Read
Write
A physical connection that incorporates the data line (pin 54 MDIO) and the clock line (pin 53 MDC).
A specific protocol that operates across the aforementioned physical connection that allows an external
controller to communicate with the KSZ8864RMN device.
Access to a set of eight 16-bit registers, consisting of 8 standard MIIM registers [0:5h], 1d and 1f MIIM
registers per port.
Preamble
Preamble
32 1’s
32 1’s
32 1’s
32 1’s
Start of Frame
Start of Frame
01
01
01
01
Table 10. Serial Management Interface (SMI) Frame Format
Table 9. MII Management Interface Frame Format
Read/Write
Read/Write
OP Code
OP Code
10
01
10
01
Bits [4:0]
Address
AAAAA
AAAAA
Bits [4:0]
Address
RR11R
RR11R
PHY
PHY
46
Bits [4:0]
Address
RRRRR
RRRRR
Bits [4:0]
Address
RRRRR
RRRRR
REG
REG
TA
Z0
10
TA
Z0
10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
Data Bits [15:0]
Bits [15:0]
Data
M9999-092011-1.4
Idle
Idle
Z
Z
Z
Z