CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 18

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

FIGURE 2.4: Block Diagram of The Timer0/WDT Prescaler
2.4 Interrupts
The CP80S54/S56 series has up to three sources of interrupt:
1.
2.
3.
INTFLAG is the interrupt flag register that recodes the interrupt requests in the relative flags.
interrupts. Individual interrupts can be enabled/disabled through their corresponding enable bits in INTEN register
regardless of the status of the GIE bit.
When an interrupt event occur with the GIE bit and its corresponding interrupt enable bit are all set, the GIE bit will
be cleared by hardware to disable any further interrupts, and the next instruction will be fetched from address 008h.
The interrupt flag bits must be cleared by software before re-enabling GIE bit to avoid recursive interrupts.
The RETFIE instruction exits the interrupt routine and set the GIE bit to re-enable interrupt.
The flag bit (except PBIF bit) in INTFLAG register is set by interrupt event regardless of the status of its mask bit.
Reading the INTFLAG register will be the logic AND of INTFLAG and INTEN.
When an interrupt is generated by the INT instruction, the next instruction will be fetched from address 002h.
2.4.1 External INT Interrupt
External interrupt on INT pin is rising or falling edge triggered selected by INTEDG (OPTION<6>).
When a valid edge appears on the INT pin the flag bit INTIF (INTFLAG<2>) is set. This interrupt can be disabled by
clearing INTIE bit (INTEN<2>).
The INT pin interrupt can wake-up the system from SLEEP condition, if bit INTIE was set before going to SLEEP. If
GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared, the
program will execute next PC after wake-up.
2.4.2 Timer0 Interrupt
An overflow (FFh
disabled by clearing T0IE bit (INTEN<0>).
A global interrupt enable bit, GIE (INTEN<7>), enables (if set) all un-masked interrupts or disables (if cleared) all
(Fosc/4 or Fosc/2 or Fosc/1 or Fosc/8)
T0CKI
Watchdog
External interrupt INT pin.
TMR0 overflow interrupt.
Port B input change interrupt (pins IOB7:IOB0).
Timer
T0SE
Instruction Cycle
00h) in the TMR0 register will set the flag bit T0IF (INTFLAG<0>). This interrupt can be
0
1
0
1
T0CS
MUX
MUX
PSA
Prescaler
PS2:PS0
8-Bit
1
0
1
0
MUX
MUX
PSA
PSA
2 Cycles
Sync
WDT Time-out
CP80S54/56
Register
TMR0
Rev0.1 Nov 30, 2005
P.18/CP80S54/S56
8
Set T0IF flag
on overflow
Data Bus