CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 30

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

CLRA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
CLRR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
COMR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
DAA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Clear ACC
CLRA
None
00h
1
Z
The ACC register is cleared. Zero bit (Z) is set.
1
Clear R
CLRR R
0
00h
1
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
CLRWDT
None
00h
00h
1
1
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is
assigned to the WDT and not Timer0. Status bits TO and PD are set.
1
Complement R
COMR R, d
0
d
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Adjust ACC’s data format from HEX to DEC
DAA
None
ACC(hex)
C
Convert the ACC data from hexadecimal to decimal format after any addition
operation and restored to ACC.
1
Clear Watchdog Timer
TO , PD
R
∈
≤
≤
R
R
[0,1]
Z
Z
PD
TO ;
≤
≤
dest
ACC;
R;
WDT;
WDT prescaler (if assigned);
63
63
ACC(dec)
CP80S54/56
Rev0.1 Nov 30, 2005
P.30/CP80S54/S56