CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 19

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

2.4.3 Port B Input Change Interrupt
An input change on IOB<7:0> set flag bit PBIF (INTFLAG<1>). This interrupt can be disabled by clearing PBIE bit
(INTEN<1>).
Before the port B input change interrupt is enabled, reading PORTB (any instruction accessed to PORTB, including
The port B input change interrupt also can wake-up the system from SLEEP condition, if bit PBIE was set before
going to SLEEP. And GIE bit also decides whether or not the processor branches to the interrupt vector following
wake-up. If GIE bit was set, the program will execute interrupt service routine after wake-up; or if GIE bit was cleared,
the program will execute next PC after wake-up.
2.5 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP instruction.
When SLEEP instruction is executed, the PD bit (STATUS<3>) is cleared, the TO bit is set, the watchdog timer will
be cleared and keeps running, and the oscillator driver is turned off.
All I/O pins maintain the status they had before the SLEEP instruction was executed.
2.5.1 Wake-up from SLEEP Mode
The device can wake-up from SLEEP mode through one of the following events:
1.
2.
3.
External RSTB reset and WDT time-out reset will cause a device reset. The PD and TO bits can be used to
determine the cause of device reset. The PD bit is set on power-up and is cleared when SLEEP instruction is
executed. The TO bit is cleared if a WDT time-out occurred.
For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set. Wake-up
is regardless of the GIE bit. If GIE bit is cleared, the device will continue execution at the instruction after the SLEEP
instruction. If the GIE bit is set, the device will branch to the interrupt address (008h).
The system wake-up delay time is 18ms plus 128 oscillator cycle time.
2.6 Reset
CP80S54/S56 devices may be RESET in one of the following ways:
1.
2.
3.
4.
Some registers are not affected in any RESET condition. Their status is unknown on Power-on Reset and
unchanged in any other RESET. Most other registers are reset to a “reset state” on Power-on Reset, RSTB or WDT
Reset.
A Power-on RESET pulse is generated on-chip when Vdd rise is detected. To use this feature, the user merely ties
the RSTB pin to Vdd.
On-chip Low Voltage Detector (LVD) places the device into reset when Vdd is below a fixed voltage. This ensures
that the device does not continue program execution outside the valid operation Vdd range. Brown-out RESET is
typically used in AC line or heavy loads switched applications.
A RSTB or WDT Wake-up from SLEEP also results in a device RESET, and not a continuation of operation before
SLEEP.
The TO and PD bits (STATUS<4:3>) are set or cleared depending on the different reset conditions.
read/write instructions) is necessary. Any pin which corresponding WUBn bit (WUCON<7:0>) is cleared to “0” or
configured as output or IOB0 pin configured as INT pin will be excluded from this function.
RSTB reset.
WDT time-out reset (if enabled).
Interrupt from RB0/INT pin, or PORTB change interrupt.
Power-on Reset (POR)
Brown-out Reset (BOR)
RSTB Pin Reset
WDT time-out Reset
CP80S54/56
Rev0.1 Nov 30, 2005
P.19/CP80S54/S56