CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 29

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

BCR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
BSR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
BTRSC
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
BTRSS
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
CALL
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
BCF R, b
0
0
0
None
Clear bit ‘b’ in register ‘R’.
1
BSR R, b
0
0
1
None
1
Test Bit in R, Skip if Clear
BTRSC R, b
0
0
Skip if R<b> = 0
None
If bit ‘b’ is 0 then next instruction fetched during the current instruction execution is discarded,
and a NOP is executed instead making this a 2-cycle instruction..
1(2)
BTRSS R, b
0
0
Skip if R<b> = 1
None
If bit ‘b’ is ‘1’, then the next instruction fetched during the current instruction execution, is
discarded and a NOP is executed instead, making this a 2-cycle instruction.
1(2)
Subroutine Call
CALL I
0
PC +1
I
PCHBUF<2>
None
Subroutine call. First, return address (PC+1) is pushed onto the stack. The 10-bit immediate
address is loaded into PC bits <9:0>. CALL is a two-cycle instruction.
2
Clear Bit in R
Set Bit in R
Set bit ‘b’ in register ‘R’.
If bit ‘b’ in register ‘R’ is 0 then the next instruction is skipped.
Test Bit in R, Skip if Set
If bit ‘b’ in register ‘R’ is ‘1’ then the next instruction is skipped.
≤
≤
≤
≤
≤
≤
≤
≤
≤
R
b
R
b
R
b
R
b
I
PC<9:0>
R<b>
R<b>
≤
≤
≤
≤
≤
≤
≤
≤
≤
1023
7
7
7
7
63
63
63
63
Top of Stack;
PC<10>
CP80S54/56
Rev0.1 Nov 30, 2005
P.29/CP80S54/S56