CP80S54E ETC2 [List of Unclassifed Manufacturers], CP80S54E Datasheet - Page 35

• Manufacturer Part Number: CP80S54E
• Description: EPROM/ROM-Based 8-Bit Microcontroller Series
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

SLEEP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SBCAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SUBAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SUBIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SWAPR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Enter SLEEP Mode
SLEEP
None
00h
00h
1
0
Time-out status bit ( TO ) is set. The power-down status bit ( PD ) is cleared. The WDT and its
prescaler are cleared.
The processor is put into SLEEP mode.
1
Subtract ACC from R with Carry
SBCAR R, d
0
d
R + ACC + C
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Subtract ACC from R
SUBAR R, d
0
d
R - ACC
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
SUBIA I
0
I - ACC
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Swap nibbles in R
SWAPR R, d
0
d
R<3:0>
R<7:4>
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
C, DC, Z
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
Subtract ACC from Immediate
C, DC, Z
TO , PD
∈
∈
∈
≤
≤
≤
≤
R
[0,1]
R
[0,1]
I
R
[0,1]
≤
PD
TO ;
≤
≤
≤
255
WDT;
WDT prescaler;
63
63
63
ACC
dest<7:4>;
dest<3:0>
dest
dest
CP80S54/56
Rev0.1 Nov 30, 2005
P.35/CP80S54/S56