MC68HC05K1 FREESCALE [Freescale Semiconductor, Inc], MC68HC05K1 Datasheet - Page 46

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MC68HC05K1

Manufacturer Part Number
MC68HC05K1
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Technical Data
4.3.2.2 PA3–PA0 Pins
Technical Data
EXTERNAL INTERRUPTS
IRQ
PA3
PA2
PA1
PA0
(MASK OPTION)
ENABLED
PORT A
The mask option for port A external interrupts enables pins PA3–PA0 to
serve as additional external interrupt sources. The PA3–PA0 pins do not
contain internal Schmitt triggers. An interrupt signal on one of the
PA3–PA0 pins latches an external interrupt request. After completing
the current instruction, the CPU tests these bits:
If both the IRQ latch and the IRQE bit are set and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
Freescale Semiconductor, Inc.
Figure 4-1. External Interrupt Logic
For More Information On This Product,
IRQF bit (IRQ latch)
IRQE bit in the interrupt status and control register
I bit in the condition code register
IRQ VECTOR FETCH
INTERNAL DATA BUS
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LEVEL-SENSITIVE TRIGGER
RST
Interrupts
V
DD
(MASK OPTION)
LATCH
IRQ
R
IRQ STATUS AND CONTROL REGISTER
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
TO BIH & BIL
INSTRUCTION
PROCESSING
EXTERNAL
INTERRUPT
REQUEST

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