MC68HC05K1 FREESCALE [Freescale Semiconductor, Inc], MC68HC05K1 Datasheet - Page 82

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MC68HC05K1

Manufacturer Part Number
MC68HC05K1
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Technical Data
8.5 COP Watchdog
Technical Data
NOTE:
Address:
Three counter stages at the end of the timer make up the mask optional
computer operating properly (COP) watchdog (see
COP watchdog is a software error detection system that automatically
times out and resets the MCU if not cleared periodically by a program
sequence. Writing a logic 0 to bit 0 of the COP register, shown in
Figure
COPC — COP Clear Bit
The COP watchdog is active in the run, wait, and halt modes of
operation. The STOP instruction disables the COP watchdog by clearing
the counter and turning off its clock source. In applications that depend
on the COP watchdog, the STOP instruction can be disabled (converted
to halt) by a mask option.
In applications that have wait cycles longer than the COP timeout period,
the COP watchdog can be disabled by a mask option.
If the voltage on the IRQ/V
watchdog turns off and remains off until the IRQ/V
2
Reset:
Read:
Write:
This write-only bit resets the COP watchdog. Reading address $03F0
returns the ROM data at that address.
Freescale Semiconductor, Inc.
V
For More Information On This Product,
DD
8-4, clears the COP watchdog and prevents a COP reset.
.
$03F0
Bit 7
U
0
Go to: www.freescale.com
= Unimplemented
Multifunction Timer
Figure 8-4. COP Register (COPR)
U
6
0
U
5
0
PP
pin exceeds a nominal 1.5 V
U = Unaffected
U
4
0
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
U
3
0
PP
U
2
0
Figure
voltage falls below
U
DD
1
1
8-1). The
, the COP
COPC
Bit 0
0
0

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