MC68HC05K1 FREESCALE [Freescale Semiconductor, Inc], MC68HC05K1 Datasheet - Page 48

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MC68HC05K1

Manufacturer Part Number
MC68HC05K1
Description
HCMOS Microcontroller Unit
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Technical Data
4.3.2.3 IRQ Status and Control Register
Technical Data
Address:
The IRQ status and control register (ISCR), shown in
contains an external interrupt mask, an external interrupt flag, and a flag
reset bit. Unused bits read as logic 0s.
IRQE — External Interrupt Request Enable Bit
IRQF — External Interrupt Request Flag
Reset:
Read:
Write:
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
The IRQF bit (IRQ latch) is a clearable, read-only bit that is set when
an external interrupt request is pending. Reset clears the IRQF bit.
These conditions set the IRQF bit:
The CPU clears the IRQF bit when fetching the interrupt vector.
Writing to the IRQF bit has no effect. Writing a logic 1 to the IRQR bit
clears the IRQF bit.
Freescale Semiconductor, Inc.
For More Information On This Product,
1 = External interrupt processing enabled
0 = External interrupt processing disabled
1 = Interrupt request pending
0 = No interrupt request pending
– An external interrupt signal on the IRQ/V
– An external interrupt signal on pin PA3, PA2, PA1, or PA0 if
Figure 4-2. IRQ Status and Control Register (ISCR)
$000A
IRQE
Bit 7
PA3–PA0 are enabled by mask option to serve as external
interrupt sources
1
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= Unimplemented
6
0
0
Interrupts
5
0
0
U = Unaffected
4
0
0
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
IRQF
3
0
PP
2
0
0
pin
Figure
IRQR
U
1
0
4-2,
Bit 0
0
0

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