PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 144

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

16.6
When the ECCP is programmed for any of the PWM
modes, the output pins associated with its function may
be configured for auto-shutdown.
Auto-shutdown allows the internal output of either of
the two comparator modules, or the external
interrupt 0, to asynchronously disable the ECCP output
pins. Thus, an external analog or digital event can
discontinue an ECCP sequence. The comparator out-
put(s) to be used is selected by setting the proper mode
bits in the ECCPAS register. To use external interrupt
INT0 as a shutdown event, INT0IE must be set. To use
either of the comparator module outputs as a shutdown
event, corresponding comparators must be enabled.
When a shutdown occurs, the selected output values
(PSSACn, PSSBDn) are written to the ECCP port pins.
REGISTER 16-3:
DS41159D-page 142
PIC18FXX8
Enhanced CCP Auto-Shutdown
bit 7
bit 6-4
bit 3-2
bit 1-0
ECCPAS: ENHANCED CAPTURE/COMPARE/PWM AUTO-SHUTDOWN
CONTROL REGISTER
ECCPASE: ECCP Auto-Shutdown Event Status bit
0 = ECCP outputs enabled, no shutdown event
1 = A shutdown event has occurred, must be reset in software to re-enable ECCP
ECCPAS<2:0>: ECCP Auto-Shutdown bits
000 = No auto-shutdown enabled, comparators have no effect on ECCP
001 = Comparator 1 output will cause shutdown
010 = Comparator 2 output will cause shutdown
011 = Either Comparator 1 or 2 can cause shutdown
100 = INT0
101 = INT0 or Comparator 1 output
110 = INT0 or Comparator 2 output
111 = INT0 or Comparator 1 or Comparator 2 output
PSSACn: Pins A and C Shutdown State Control bits
00 = Drive Pins A and C to ‘0’
01 = Drive Pins A and C to ‘1’
1x = Pins A and C tri-state
PSSBDn: Pins B and D Shutdown State Control bits
00 = Drive Pins B and D to ‘0’
01 = Drive Pins B and D to ‘1’
1x = Pins B and D tri-state
bit 7
ECCPASE ECCPAS2 ECCPAS1 ECCPAS0
Legend:
R = Readable bit
-n = Value at POR
R/W-0
R/W-0
R/W-0
W = Writable bit
‘1’ = Bit is set
R/W-0
The internal shutdown signal is gated with the outputs
and will immediately and asynchronously disable the
outputs. If the internal shutdown is still in effect at the
time a new cycle begins, that entire cycle is
suppressed, thus eliminating narrow, glitchy pulses.
The ECCPASE bit is set by hardware upon a compara-
tor event and can only be cleared in software. The
ECCP outputs can be re-enabled only by clearing the
ECCPASE bit.
The Auto-Shutdown mode can be manually entered by
writing a ‘1’ to the ECCPASE bit.
PSSAC1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
PSSAC0
R/W-0
 2004 Microchip Technology Inc.
x = Bit is unknown
PSSBD1
R/W-0
PSSBD0
R/W-0
bit 0