PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 274

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

24.2
The Watchdog Timer is a free running, on-chip RC
oscillator which does not require any external com-
ponents. This RC oscillator is separate from the RC
oscillator of the OSC1/CLKI pin. That means that the
WDT will run, even if the clock on the OSC1/CLKI and
OSC2/CLKO/RA6 pins of the device has been stopped,
for example, by execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device Reset (Watchdog Timer Reset). If the device is
in Sleep mode, a WDT time-out causes the device to
wake-up
(Watchdog Timer wake-up). The TO bit in the RCON
register will be cleared upon a WDT time-out.
The Watchdog Timer is enabled/disabled by a device
configuration bit. If the WDT is enabled, software
execution may not disable this function. When the
WDTEN configuration bit is cleared, the SWDTEN bit
enables/disables the operation of the WDT.
REGISTER 24-13: WDTCON: WATCHDOG TIMER CONTROL REGISTER
DS41159D-page 272
PIC18FXX8
Watchdog Timer (WDT)
and
bit 7-1
bit 0
continue
bit 7
Unimplemented: Read as ‘0’
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if the WDTEN configuration bit in the Configuration register = 0
Legend:
R = Readable bit
U = Unimplemented bit, read as ‘0’
U-0
—
with
normal
U-0
—
operation
U-0
—
U-0
—
The WDT time-out period values may be found in
Section 27.0 “Electrical Characteristics” under
parameter #31. Values for the WDT postscaler may be
assigned using the configuration bits.
24.2.1
Register 24-13 shows the WDTCON register. This is a
readable and writable register which contains a control
bit that allows software to override the WDT enable
configuration bit only when the configuration bit has
disabled the WDT.
W = Writable bit
-n = Value at POR
Note:
Note:
U-0
—
The CLRWDT and SLEEP instructions clear
the WDT and the postscaler if assigned to
the WDT and prevent it from timing out
and generating a device Reset condition.
When a CLRWDT instruction is executed
and the postscaler is assigned to the WDT,
the postscaler count will be cleared but the
postscaler assignment is not changed.
CONTROL REGISTER
U-0
—
 2004 Microchip Technology Inc.
U-0
—
SWDTEN
R/W-0
bit 0