PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 52

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

TABLE 4-2:
DS41159D-page 50
PIC18FXX8
TMR1H
TMR1L
T1CON
TMR2
PR2
T2CON
SSPBUF
SSPADD
SSPSTAT
SSPCON1
SSPCON2
ADRESH
ADRESL
ADCON0
ADCON1
CCPR1H
CCPR1L
CCP1CON
ECCPR1H
ECCPR1L
ECCP1CON
ECCP1DEL
ECCPAS
CVRCON
CMCON
TMR3H
TMR3L
T3CON
SPBRG
RCREG
TXREG
TXSTA
RCSTA
EEADR
EEDATA
EECON2
EECON1
IPR3
PIR3
PIE3
IPR2
PIR2
PIE2
Legend:
Note
File Name
1:
2:
3:
(1)
(1)
(1)
(1)
(1)
(1)
(1)
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
Bit 21 of the TBLPTRU allows access to the device configuration bits.
RA6 and associated bits are configured as port pins in RCIO and ECIO Oscillator mode only and read ‘0’ in all other oscillator modes.
Timer1 Register High Byte
Timer1 Register Low Byte
Timer2 Register
Timer2 Period Register
SSP Receive Buffer/Transmit Register
SSP Address Register in I
A/D Result Register High Byte
A/D Result Register Low Byte
Capture/Compare/PWM Register 1 High Byte
Capture/Compare/PWM Register 1 Low Byte
Enhanced Capture/Compare/PWM Register 1 High Byte
Enhanced Capture/Compare/PWM Register 1 Low Byte
Timer3 Register High Byte
Timer3 Register Low Byte
USART Baud Rate Generator
USART Receive Register
USART Transmit Register
EEPROM Address Register
EEPROM Data Register
EEPROM Control Register 2 (not a physical register)
EPWM1M1
ECCPASE
CVREN
C2OUT
EEPGD
ADCS1
EPDC7
WCOL
GCEN
CSRC
ADFM
SPEN
RD16
RD16
IRXIP
IRXIF
IRXIE
Bit 7
SMP
—
—
—
—
—
REGISTER FILE SUMMARY (CONTINUED)
EPWM1M0
TOUTPS3
ECCPAS2
ACKSTAT
T3ECCP1
CVROE
SSPOV
ADCS0
ADCS2
EPDC6
C1OUT
WAKIP
WAKIF
WAKIE
CFGS
CMIP
CMIF
CMIE
Bit 6
CKE
RX9
TX9
—
—
2
C™ Slave mode. SSP Baud Rate Reload Register in I
T1CKPS1
TOUTPS2
ECCPAS1
T3CKPS1
EDC1B1
SSPEN
ACKDT
DC1B1
EPDC5
ERRIP
ERRIE
C2INV
ERRIF
CVRR
SREN
CHS2
TXEN
Bit 5
D/A
—
—
—
—
—
TOUTPS1
ECCPAS0
T1CKPS0
T3CKPS0
EDC1B0
ACKEN
CVRSS
EPDC4
TXB2IP
TXB2IF
TXB2IE
DC1B0
C1INV
SYNC
CREN
CHS1
FREE
EEIP
EEIF
EEIE
Bit 4
CKP
—
P
T1OSCEN
ECCP1M3
TOUTPS0
CCP1M3
PSSAC1
T3CCP1
WRERR
SSPM3
ADDEN
TXB1IP
TXB1IF
TXB1IE
PCFG3
EPDC3
BCLIP
BCLIF
BCLIE
RCEN
CHS0
CVR3
Bit 3
CIS
—
S
GO/DONE
ECCP1M2
TMR2ON
CCP1M2
T1SYNC
PSSAC0
T3SYNC
SSPM2
PCFG2
EPDC2
TXB0IP
TXB0IF
TXB0IE
WREN
BRGH
LVDIP
LVDIE
CVR2
FERR
LVDIF
Bit 2
CM2
R/W
PEN
2
C Master mode.
ECCP1M1 ECCP1M0 0000 0000
T2CKPS1
TMR1CS
TMR3CS
CCP1M1
PSSBD1
RXB1IP
RXB1IE
TMR3IP
TMR3IF
TMR3IE
SSPM1
RXB1IF
PCFG1
EPDC1
OERR
RSEN
CVR1
TRMT
Bit 1
CM1
WR
UA
—
 2004 Microchip Technology Inc.
ECCP1IP
ECCP1IF
ECCP1IE
T2CKPS0 -000 0000
TMR1ON
TMR3ON
CCP1M0
PSSBD0
RXB0IP
RXB0IE
SSPM0
PCFG0
EPDC0
RXB0IF
ADON
CVR0
RX9D
TX9D
Bit 0
CM0
SEN
RD
BF
(1)
(1)
(1)
xxxx xxxx
xxxx xxxx
0-00 0000
0000 0000
1111 1111
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 00-0
00-- 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
0000 -010
0000 000x
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx-0 x000 32, 60, 67
1111 1111
0000 0000
0000 0000
-1-1 1111
-0-0 0000
-0-0 0000
POR, BOR
Value on
Details on
31, 144,
31, 145,
31, 146
31, 152
31, 155
31, 243
31, 243
31, 241
32, 242
32, 124
32, 124
32, 123
32, 133
32, 133
32, 131
32, 140
32, 142
32, 255
32, 249
32, 121
32, 121
32, 185
32, 191
32, 189
32, 183
32, 184
31, 116
31, 116
31, 113
31, 118
31, 118
31, 117
32, 119
32, 59
32, 59
32, 59
32, 90
32, 84
32, 87
32, 89
32, 83
32, 86
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