PIC18F24 MICROCHIP [Microchip Technology], PIC18F24 Datasheet - Page 195

• Manufacturer Part Number: PIC18F24
• Description: 28/40-Pin High-Performance, Enhanced Flash Microcontrollers with CAN Module
• Manufacturer: MICROCHIP [Microchip Technology]

18.3
In Synchronous Master mode, the data is transmitted in
a half-duplex manner (i.e., transmission and reception
do not occur at the same time). When transmitting data,
the reception is inhibited and vice versa. Synchronous
mode is entered by setting bit SYNC (TXSTA register).
In addition, enable bit SPEN (RCSTA register) is set in
order to configure the RC6/TX/CK and RC7/RX/DT I/O
pins to CK (clock) and DT (data) lines, respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting bit CSRC (TXSTA register).
18.3.1
The USART transmitter block diagram is shown in
Figure 18-1. The heart of the transmitter is the Transmit
(Serial) Shift Register (TSR). The shift register obtains
its data from the Read/Write Transmit Buffer register
(TXREG). The TXREG register is loaded with data in
software. The TSR register is not loaded until the last
bit has been transmitted from the previous load. As
soon as the last bit is transmitted, the TSR is loaded
with new data from the TXREG (if available). Once the
TXREG register transfers the data to the TSR register
(occurs in one T
bit TXIF (PIR1 register) is set. The interrupt can be
enabled/disabled by setting/clearing enable bit TXIE
(PIE1 register). Flag bit TXIF will be set regardless of
the state of enable bit TXIE and cannot be cleared in
TABLE 18-8:
 2004 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
TXREG
TXSTA
SPBRG
Legend:
Note 1:
Name
USART Synchronous
Master Mode
USART Transmit Register
Baud Rate Generator Register
GIE/GIEH PEIE/GIEL TMR0IE
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master transmission.
These registers or register bits are not implemented on the PIC18F248 and PIC18F258 and read as ‘0’s.
PSPIF
PSPIE
PSPIP
USART SYNCHRONOUS MASTER
TRANSMISSION
CSRC
SPEN
Bit 7
CY
(1)
(1)
(1)
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION
), the TXREG is empty and interrupt
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
SREN
TXEN
RCIF
RCIE
RCIP
Bit 5
INT0IE
CREN
SYNC
Bit 4
TXIF
TXIE
TXIP
ADDEN
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
—
TMR0IF
CCP1IE
CCP1IP
CCP1IF
BRGH
FERR
Bit 2
software. It will reset only when new data is loaded into
the TXREG register. While flag bit, TXIF, indicates the
status of the TXREG register, another bit, TRMT
(TXSTA register), shows the status of the TSR register.
TRMT is a read-only bit which is set when the TSR is
empty. No interrupt logic is tied to this bit, so the user
has to poll this bit in order to determine if the TSR
register is empty. The TSR is not mapped in data
memory, so it is not available to the user.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
Note:
Initialize the SPBRG register for the appropriate
baud rate (Section 18.1 “USART Baud Rate
Generator (BRG)”).
Enable the synchronous master serial port by
setting bits SYNC, SPEN and CSRC.
If interrupts are desired, set enable bit TXIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting bit TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the TXREG
register.
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
Bit 1
TXIF is not cleared immediately upon
loading data into the transmit buffer
TXREG. The flag bit becomes valid in the
second instruction cycle following the load
instruction.
TMR1IF
TMR1IE
TMR1IP
RX9D
TX9D
RBIF
Bit 0
PIC18FXX8
0000 000x
0000 0000
0000 0000
1111 1111
0000 000x
0000 0000
0000 -010
0000 0000
POR, BOR
Value on
DS41159D-page 193
0000 000u
0000 0000
0000 0000
1111 1111
0000 000u
0000 0000
0000 -010
0000 0000
Value on
all other
Resets