PIC18F2525 MICROCHIP [Microchip Technology], PIC18F2525 Datasheet - Page 43
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PIC18F2525
Manufacturer Part Number
PIC18F2525
Description
28/40/44-Pin Enhanced Flash Microcontrollers with 10-Bit A/D and nanoWatt Technology
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
1.PIC18F2525.pdf
(390 pages)
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4.0
The PIC18F2525/2620/4525/4620 devices differentiate
between various kinds of Reset:
a)
b)
c)
d)
e)
f)
g)
h)
This section discusses Resets generated by MCLR,
POR and BOR and covers the operation of the various
start-up timers. Stack Reset events are covered in
Section 5.1.2.4 “Stack Full and Underflow Resets”.
WDT Resets are covered in Section 23.2 “Watchdog
Timer (WDT)”.
FIGURE 4-1:
2004 Microchip Technology Inc.
Note 1: This is the INTRC source from the internal oscillator block and is separate from the RC oscillator of the CLKI pin.
OSC1
MCLR
V
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during power managed modes
Watchdog Timer (WDT) Reset (during
execution)
Programmable Brown-out Reset (BOR)
RESET Instruction
Stack Full Reset
Stack Underflow Reset
DD
2: See Table 4-2 for time-out situations.
RESET
Instruction
INTRC
RESET
OST/PWRT
Pointer
32 s
Stack
Brown-out
( )_IDLE
Time-out
V
(1)
Detect
Sleep
DD
WDT
Reset
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
Stack Full/Underflow Reset
External Reset
MCLRE
10-bit Ripple Counter
11-bit Ripple Counter
POR Pulse
BOREN
1024 Cycles
65.5 ms
PIC18F2525/2620/4525/4620
Preliminary
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 4-1.
4.1
Device Reset events are tracked through the RCON
register (Register 4-1). The lower five bits of the regis-
ter indicate that a specific Reset event has occurred. In
most cases, these bits can only be cleared by the event
and must be set by the application after the event. The
state of these flag bits, taken together, can be read to
indicate the type of Reset that just occurred. This is
described in more detail in Section 4.6 “Reset State
of Registers”.
The RCON register also has control bits for setting
interrupt priority (IPEN) and software control of the
BOR (SBOREN). Interrupt priority is discussed in
Section 9.0
Section 4.4 “Brown-out Reset (BOR)”.
RCON Register
“Interrupts”.
S
R
BOR
DS39626B-page 41
Q
is
Enable OST
Enable PWRT
Chip_Reset
covered
(2)
in
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